Paolo Ienne has been a professor at EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to joining EPFL, he worked for the Semiconductors Group of Siemens AG in Munich, Germany, which later became Infineon Technologies AG, where he headed the Embedded Memories Unit in the Design Libraries Division. His research interests include computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. His work has received nine Best Paper Awards: at the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) in 2012, 2016, and 2020; at the International Conference on Field-Programmable Logic and Applications (FPL) in 2009, 2020, 2021, and 2024; at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) in 2007; and at the Design Automation Conference (DAC) in 2003. Several further papers have been nominated for Best Paper Awards at major conferences. He has served as general, programme, and topic chair of renowned international conferences, including as General Co-chair of FPL 2016 in Lausanne. He chairs the Steering Committee of FPL and serves on the steering committees of FPGA and the IEEE Symposium on Computer Arithmetic (ARITH). He has guest-edited several special issues and sections for IEEE and ACM journals and regularly serves on the programme committees of international conferences and workshops in design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an Associate Editor of ACM Computing Surveys (CSUR) since 2014 and previously served as an Associate Editor of ACM Transactions on Architecture and Code Optimization (TACO) from 2015 to 2026 and ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.