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Alessandro Cevrero
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Doctoral Program in Microsystems and Microelectronics
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birth date: 09.06.1983
nationality: Italian
web site:
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private phone: +41216936937/ +393494463482
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MISSION
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Eliminating the performance gap between FPGAs and ASICSs has been a major focus of both industrial FPGAs vendors as well as academic researchers. Alessandro Cevrero Research attempts to address the discrepancies between FPGAs and ASICs by proposing a novel reconfigurable lattice that accelerates the core operation of many arithmetic application: multi-operand addition. This lattice, called a Field Programmable Counter Array(FPCA), can be viewed by the designer as a programmable IP core.
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BIOGRAPHY
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Alessandro Cevrero Received the B.S degree in electrical Enginnering from Politecnico di Torino in 2005. He received an M.S. Degree in Micro- and Nano-technologies for Integrated Systems, issued jointly from the INP Grenoble, Politecnico di Torino, and EPFL in 2007. In October 2007, he joined both the Microelectronics Systems Laboratory and the Processor Architecture Laboratory at EPFL as research assistant and worked in the field of digital VLSI design. He will start his PhD at EPFL in March, 2008. His research interests include digital VLSI design, the design and implementation of high speed arithmetic blocks, reconfigurable datapaths, and computer architecture.
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Submitted/Under Review Publications
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Architectural Improvements for Field Programmable Counter Arrays:
Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs.
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar,
Ajay K. Verma,Philip Brisk, Frank K. Gurkaynak, Yusuf Leblebici, Paolo
Ienne.
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Alessandro.cevrero@hotmail.it
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| gmail account |
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cevrero.alessandro@gmail.com
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Student