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Seyed Armin Tajalli BIOGRAPHY Armin Tajalli received the B.S.E.E. and M.S.E.E degrees (with honors) from Sharif University of Technology, Tehran, and Tehran Polytechnic University in 1997, and 1999, respectively. He has received his Ph.D.E.E. on low-power integrated circuit design techniques in 2010 from Swiss Federal Institute of Technology (EPFL). He was with Emad Semicon during 1998-2006 as a senior analog/RF design engineer and technical manager. From 2006 he has joined Microelectronic Systems Laboratory (LSM) in Swiss Federal Institute of Technology in Lausanne (EPFL) working on design of ultra-low power circuits, high speed serial links, and circuits for RFID systems. From 2010 he has been with ALGO team developing architectures and circuits for very high-speed and very power-efficient serial data transceivers (Kandou signaling method). He has received the Kharazmi Award on Research and Development, 2000, Outstanding Design Engineer, Emad Semicon, 2001, Presidential Award of the best Iranian researchers, 2003, ACM/CICC Award, 2009, and EPFL Prime Special Award, 2009. He has served as a technical program committee member in IEEE International Conference on Computer Design (ICCD), 2010. Professional course Senior Analog Design Engineer, Telecommunication IC Design Group, Emad Semicon, 1998-2005 Technical Manager, RF IC Design Group, Emad Semicon, 2005-2006 Research Associate, Microelectronic Systems Lab (LSM), Ecole Polytechnique Fédérale de Lausanne (EPFL), 2006-2010 Post Doctoral Fellow, ALGO, Ecole Polytechnique Fédérale de Lausanne (EPFL), 2010 - now MISSION My work has been mainly focused on design and implementation of high-performance and low-power integrated circuits. Developing design techniques for implementing ultra-low power integrated systems, reconfigurable analog circuits, very high-speed circuit for telecommunication systems, and dynamic power-speed control are some of the main topics that recently I have been working on. MAIN PUBLICATIONS A. Tajalli and Y. Leblebici. Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. Ieee Transactions On Circuits And Systems I-Regular Papers, 58:2189-2200, 2011. [ DOI | Details ] A. Tajalli and Y. Leblebici. Design trade-offs in ultra-low-power CMOS and STSCL digital systems. In Proceedings of 20th European Conference on Circuit Theory and Design, pages 544-547, Linköping, Sweden, 2011. [ Details ] A. Tajalli and Y. Leblebici. Power and Area Efficient MOSFET-C Filter for Very Low Frequency Applications. Analog Integrated Circuits and Signal Processing, 2011. [ DOI | Details | Full Text ] A. Tajalli and Y. Leblebici. Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Transactions on Circuits and Systems Part 2 Express Briefs, 58(3):159-163, 2011. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS. IEEE Transactions on Circuits and Systems-I: Regular Papers, 58(9):2189-2200, 2011. [ DOI | Details | Full Text | Link ] A. Tajalli, M. Chahardori, and A. Khodaverdi. An area and power optimization technique for CMOS bandgap voltage references. Analog Integrated Circuits And Signal Processing, 62:131-140, 2010. [ DOI | Details ] A. Tajalli and Y. Leblebici. Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits. Springer, 2010. [ Details | Link ] S. A. Tajalli, Y. Leblebici, and E. A. Vittoz. Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS. PhD thesis, Lausanne, 2010. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems. In Proceedings of the European Solid-State Circuits Conference (ESSCIRC), 2010. [ Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution. In Proceedings of the European Solid-State Circuits Conference (ESSCIRC), 2010. [ Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits. Journal of Low Power Electronics (JOLPE), 6(1):211-217, 2010. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits. In Proceedings of Design, Automation, & Test in Europe (DATE). DATE, 2010. [ Details | Full Text | Link ] A. Tajalli, M. Alioto, E. J. Brauer, and Y. Leblebici. Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. In Integrated Circuit And Systems Design: Power And Timing Modeling, Optimization And Simulation, volume 5349 of Lecture Notes In Computer Science, pages 21-30. Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa, 2009. [ Details ] A. Tajalli and Y. Leblebici. Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems. In Proceedings of the European Solid-State Circuits Conference (ESSCIRC), pages 164-167, Athens, Greece, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold. In Proceedings of the Custom Integrated Circuits Conference (CICC), pages 593-596. IEEE, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Transaction on Circuits and Systems-II, 56(5):347-351, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli, E. Brauer, and Y. Leblebici. Ultra-Low Power 32-bit Pipelined Adder Using Subthreshold Source-Coupled Logic with 5fJ/stage PDP. Microelectronics Journal, 40(6):973-978, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pages 2553-2556. IEEE, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology. IEEE Journal of Solid-State Circuits, 44(2):538-548, 2009. [ DOI | Details | Full Text | Link ] A. Tajalli, M. Alioto, and Y. Leblebici. Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits. IEEE Transaction on Circuits and Systems-II, 56(2):127-131, 2009. [ DOI | Details | Full Text | Link ] P. Sakian, M. Saffari, M. Atarodi, and A. Tajalli. Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance. Iet Circuits Devices & Systems, 2:409-421, 2008. [ DOI | Details ] T. Liechti, A. Tajalli, O. C. Akgun, Z. Toprak, and Y. Leblebici. A 1.8v 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology. In IEEE Asia-Pacific Conference on Circutis and Systems, pages 21-24, China, 2008. IEEE. [ DOI | Details | Full Text | Link ] M. Beikahmadi, A. Tajalli, and Y. Leblebici. A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC. In Proceedings of NORCHIP, pages 9-12, Tallinn, Estonia, 2008. NORCHIP. [ DOI | Details | Full Text | Link ] A. Tajalli, Y. Leblebici, and E. J. Brauer. Pico-Watt Source-Coupled Logic Circuits. In 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Greece, 2008. [ Details | Full Text | Link ] L. Svensson, J. Monteiro, A. Tajalli, M. Alioto, E. Brauer, and Y. Leblebici. Improving the power-delay performance in subthreshold source-coupled logic circuits. In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Integrated Circuit and System Design, pages 21-30, Portugal, 2008. Springer. [ Details | Full Text | Link ] A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz. Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications. IEEE Journal of Solid-State Circuits, 43(7):1699 - 1710, 2008. [ DOI | Details | Full Text | Link ] A. Tajalli, F. K. Gurkaynak, Y. Leblebici, M. Alioto, and E. J. Brauer. Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage. In Proceedings of the International Symposum on Circuits and Systems (ISCAS), pages 145 - 148, Seattle, Washington, USA, 2008. IEEE. [ DOI | Details | Full Text | Link ] A. Tajalli, Y. Leblebici, and E. J. Brauer. Implementing Ultra-high-Value Floating Tunable CMOS Resistors. IEE Electronics Letters, 44(5):349-350, 2008. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. Wide tuning range linearity improved biquadratic transconductor-C filter. IEE Electronics Letters, 43(24):1360-1362, 2007. [ DOI | Details | Full Text | Link ] A. Tajalli, P. Muller, and Y. Leblebici. Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits. J. of Low-Power Electronics, 3(3):345-354, 2007. [ DOI | Details | Full Text | Link ] A. Tajalli, P. Muller, and Y. Leblebici. A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE Journal of Solid-State Circuits, 42(10):2235-2244, 2007. [ DOI | Details | Full Text | Link ] A. Tajalli, E. Vittoz, Y. Leblebici, and E. Brauer. Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device. IEE Electronics Letters, 43(17):911-913, 2007. [ DOI | Details | Full Text | Link ] A. Tajalli and Y. Leblebici. A Power-Efficient LVDS Driver Circuit in 0.18-um CMOS Technology. In Proceedings of 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pages 145-148, Bordeaux, 2007. [ Details | Full Text | Link ] A. Tajalli, Y. Leblebici, E. Vittoz, and E. J. Brauer. Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept. In Proceedings of the 33rd European Solid-State Circuits Conference (ESSCIRC), 2007. [ DOI | Details | Full Text | Link ] A. Tajalli, P. Muller, M. Atarodi, and Y. Leblebici. Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. In Proceedings of the International Symposium on Circuits and Systems (ISCAS), pages 2109-2112. IEEE, 2006. [ DOI | Details | Full Text | Link ] P. Muller, M. K. Emsley, A. Tajalli, M. Ataraodi, M. S. Unlü, and Y. Leblebici. Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links. In proceedings of the 32nd European Solid-State Circuits Conference (ESSCIRC), pages 480-483. IEEE, 2006. [ DOI | Details | Full Text | Link ] A. Tajalli, P. Muller, M. Atarodi, and Y. Leblebici. A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology. In Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC), pages 193-196, 2005. [ DOI | Details | Full Text | Link ] A. Tajalli, P. Muller, M. Atarodi, and Y. Leblebici. A low-power, multichannel gated oscillator-based CDR for short-haul applications. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 107-110, 2005. [ Details | Full Text | Link ] P. Muller, A. Tajalli, M. Atarodi, and Y. Leblebici. Top-Down Design of a Low-Power Multi-Channel 2.5-gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. In Proceedings of Design, Automation and Test in Europe (DATE), volume 1, pages 258 - 263. IEEE, 2005. [ DOI | Details | Full Text | Link ]

Skills -Ultra Low Power Circuits -Analog/Mixed-Signal Circuits -Data Converters -Serial Data Transceivers -Clock and Data Recovery -Phase-locked loop -RFID -RF/high-frequency circuits Teaching Electrical and Electronics Engineering VLSI design II [en] (SSC SEL SIN) Mailing Address EPFL STI IEL LSM ELD 335 (Bâtiment EL) Station 11 CH-1015 Lausanne Switzerland Contact ph +41 21 693 1316 fx +41 21 693 6959