français | english		EPFL > people@EPFL > Ciprian Seiculescu login

Student ETU EDOC EDIC Doctoral Assistant IC ISIM LSI1

Ciprian Seiculescu Doctoral Program in Computer, Communication and Information Sciences office(s): INF339 phone(s): [+41 21 69] 30916 BIOGRAPHY MSc: in Computer Science, January 2008, from Ecole Polytechnique Federale de Lausanne. Graduation project: “Design Framework and Methodology for Synthesis of Networks-On-Chip on FPGA Platforms and 3D Chips”. BSc: in Automation and Computer Science, September 2006, from ‘Politehnica’ University of Timisoara, Romania. Graduation project: "3D Multi-Material Printing: Control of the Printing Heads". The work for the graduation project was done at Fraunhofer IPA in Stuttgart, Germany. MAIN PUBLICATIONS A. Sheibanyrad, F. Pétrot, A. Jantsch, C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. 3d Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks. In 3D Integration for NoC-based SoC Architectures, number 3, pages 193-223. Springer New York, 2011. [ DOI | Details ] C. Silvano, M. Lajolo, G. Palermo, C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. In Low Power Networks-on-Chip, number 3, pages 199-222. Springer New York, 2011. [ DOI | Details ] C. Seiculescu, S. Volos, N. Khosro Pour, B. Falsafi, and G. De Micheli. CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips. In Proceedings of the Workshop on Energy-Efficient Design (WEED 2011), 2011. [ Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. A DRAM Centric NoC Architecture and Topology Design Approach. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 54-59, 2011. [ Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(12):1987-2000, 2010. [ DOI | Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(5):364 - 368, 2010. [ DOI | Details | Full Text ] G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, and A. Pullini. Networks on Chips: from Research to Products. In Proceedings of the 47th Design Automation Conference (DAC 2010), volume 1, pages 300-305, 2010. [ Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control. In Proceedings of the Design, Automation and Test in Europe Conference (DATE 2010), 2010. [ Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs. In DAC 2009, pages 822-825, 2009. [ Details | Full Text ] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli. SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip. In DATE 2009, pages 9-14, 2009. [ Details | Full Text ] S. Murali, C. Seiculescu, L. Benini, and G. De Micheli. Synthesis of Networks on Chips for 3D Systems on Chips. In Asian and South Pacific Design Automation Conference, ASPDAC 2009, pages 242-247, 2009. [ Details | Full Text ] OTHER PUBLICATIONS Reza Kakoee, M.; Angiolin, F.; Murali, S.; Pullini, A.; Seiculescu, C.; Benini, L. "A floorplan-aware interactive tool flow for NoC design and synthesis", IEEE International SOC Conference 2009, page(s): 379 - 382