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Davide Garetto
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office(s):
ELD333
phone(s): [+41 21 69] 34698
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BIOGRAPHY
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Davide Garetto is a PhD candidate enrolled in EPFL and working full-time in the IBM Systems & Technology group at the ST Microelectronics R&D center in Crolles (Grenoble - France). His research activity involves the modeling and IC design of advanced MOS devices in embedded non-volatile memory technologies, with emphasis on floating gate transistors and flash cells. His goal is the development of a new physically-based compact model for eNVM devices and his project involves analytical and optimized modeling, TCAD simulations, test structures and IC design and electrical characterization with full automated testers and dedicated workbenches. He has been awarded the prestigious IBM PhD fellowship for the year 2010-2011.
A native of Torino, in Italy, Davide Garetto earned his Bachelor's Degree in Computer engineering with honors at the Politecnico di Torino in 2006, and his joint Master's Degree in Micro and Nanoelectronics with honors at the Politecnico di Torino, INP Grenoble and EPFL in 2008. He first joined IBM Research in 2008 to carry out his master's thesis project in the IBM Almaden Research Center, San Jose - California on modeling of phase change memory devices. After completing his master's degree, he returned to IBM to pursue his PhD.
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Education
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Master's degree in Micro and Nanotechnologies for Integrated Systems, Microelectronics, Politecnico di Torino - INP Grenoble - EPFL,
Bachelor Degree in Computer Engineering, Computer Engineering, Politecnico di Torino, 2003-2006
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MAIN PUBLICATIONS
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D. Garetto, A. Zaka, V. Quenette, D. Rideau, E. Dornel, W. F. Clark,
M. Minondo, C. Tavernier, Q. Rafhay, R. Clerc, A. Schmid, Y. Leblebici, and
H. Jaouen.
Embedded non–volatile memory study with surface potential based
model.
In International Workshop on Compact Modeling 2009
(Nanotech 2009), 2009.
[ Details |
Full Text |
Link ]
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D. Garetto, E. Dornel, S. Hniki, D. Rideau, W. F. Clark, A. Schmid,
C. Tavernier, H. Jaouen, and Y. Leblebici.
Analytical and compact models of the ONO capacitance in embedded
non-volatile flash devices.
In European Solid-State Devices and Technologies
Conference, ESSDERC/ESSCIRC Fringe Poster Session, 2009.
[ Details |
Full Text |
Link ]
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D. Garetto, D. Rideau, E. Dornel, W. F. Clark, C. Tavernier, Y. Leblebici,
A. Schmid, and H. Jaouen.
Modeling study of capacitance and gate current in strained
High–K Metal gate technology: impact of Si/SiO2/HK
interfacial layer and band structure model.
In 13th International Nanotech Conference and Expo
2010.
[ Details ]
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| Skills |
Analytical modeling
Compact modeling
FEM & FDTD analysis
TCAD simulation methods
IC design
Electrical characterization |
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Student