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Doctoral Assistant STI IEL LSM Doctoral Assistant IC ISIM LSI1 Student ETU EDOC EDMI

Davide Sacchetto office(s): ELD337 phone(s): [+41 21 69] 36922 BIOGRAPHY Davide Sacchetto received the B.S. degree in physics engineering from Politecnico di Torino (Italy) in 2007. In 2008 he received the jointed M.S. degree in Micro and Nano Technologies for Integrated Systems from École Polytechnique Fédérale de Lausanne, the Institut National Polytechnique de Grenoble and the Politecnico di Torino. Since November 2008 he is working as a Ph.D. student at the Microelectronic System Laboratory (LSM) and the Integrated System Laboratory (LSI), EPFL. His research interests focus on novel devices, investigating issues ranging from solid-state microfabrication to circuit implementation. MAIN PUBLICATIONS D. Sacchetto, M. Zervas, Y. Temiz, G. De Micheli, and Y. Leblebici. Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics. IEEE Transactions on Nanotechnology, 11(1):8-11, 2012. [ DOI | Details | Full Text ] D. Sacchetto, G. De Micheli, and Y. Leblebici. Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability. IEEE Electron Device Letters, 2011. [ DOI | Details | Full Text ] M. Zervas, D. Sacchetto, G. De Micheli, and Y. Leblebici. Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget. Microelectronic Engineering, 88(10):3127-3132, 2011. [ DOI | Details | Full Text ] D. Sacchetto, A. V. Savu, G. De Micheli, J. Brugger, and Y. Leblebici. Ambipolar silicon nanowire FETs with stenciled-deposited metal gate. Microelectronic Engineering, 88:2732-2735, 2011. [ DOI | Details | Full Text ] D. Sacchetto, M. De Marchi, G. De Micheli, and Y. Leblebici. Alternative Design Methodologies for the Next Generation Logic Switch (invited paper). In International Conference on Computer-Aided Design (ICCAD-2011), 2011. Invited Paper. [ DOI | Details | Full Text ] E. F. Arkan, D. Sacchetto, I. Yildiz, Y. Leblebici, and B. E. Alaca. Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications. Journal of Micromechanics and Microengineering, 2011. [ DOI | Details ] D. Sacchetto, S. Xie, A. V. Savu, M. Zervas, G. De Micheli, J. Brugger, and Y. Leblebici. Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography. In Proceedings of the 37th International Conference on Micro and Nano Engineering (MNE), 2011. [ Details ] H. Ben-Jamaa, P.-E. Gaillardon, F. Clermidy, I. O'Connor, D. Sacchetto, G. De Micheli, and Y. Leblebici. Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications. Science of Advanced Materials, 3:466-476, 2011. [ DOI | Details | Full Text ] D. Sacchetto, M.-A. Doucey, G. De Micheli, Y. Leblebici, and S. Carrara. New Insight on Bio-sensing by Nano-fabricated Memristors. BioNanoScience, 1(1-2):1-3, 2011. [ DOI | Details | Full Text ] D. Sacchetto, H. Ben Jamaa, B. Shashi Kanth, and F. Sun. Emerging Interconnect Technologies. In Communication Architectures for Systems-On-Chip. CRC Press Taylor & Francis Group, 6000 Broken Sound Parkway NW, Suite 300, 2011. [ Details ] D. Sacchetto, G. De Micheli, and Y. Leblebici. Ambipolar Si Nanowire Field Effect Transistors for Low Current and Temperature Sensing. In Proceedings of the 16th International Conference on Solid-State Sensors, Actuators and Microsystems, 2011. [ Details | Full Text ] D. Sacchetto, A. V. Savu, G. De Micheli, J. Brugger, and Y. Leblebici. Ambipolar Silicon Nanowire FETs with Stenciled-Deposited Metal Gate. Microelectronic Engineering, 88(8):2732-2735, 2011. [ DOI | Details | Full Text ] D. Sacchetto, A. V. Savu, G. De Micheli, J. Brugger, and Y. Leblebici. Ambipolar Silicon Nanowire FETs with Stenciled-Deposited Metal Gate, Microelectronic Engineering. In Proceedings of the 36th Conference on Micro and Nano Engineering, 2010. [ Details | Full Text ] D. Sacchetto, H. Ben-Jamaa, S. Carrara, G. De Micheli, and Y. Leblebici. Memristive Devices Fabricated with Silicon Nanowire Schottky Barrier Transistors. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), volume 1 of IEEE International Symposium on Circuits and Systems, pages 9-12. Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa, 2010. [ Details | Full Text ] D. Sacchetto, H. Ben-Jamaa, G. De Micheli, and Y. Leblebici. Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), volume 1 of IEEE International Symposium on Circuits and Systems, pages 1715-1717. Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa, 2010. [ Details | Full Text ] D. Sacchetto, M. H. Ben Jamaa, G. De Micheli, and Y. Leblebici. Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays. In Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC), 2009. [ Details | Full Text ]