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Hu Xu
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Doctoral Program in Computer, Communication and Information Sciences
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PhD Candidate
nationality: Chinese
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office(s):
INF335
phone(s): [+41 21 69] 37214
private phone: +41-78-6815624
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BIOGRAPHY
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XU Hu was born in Nanning, Guangxi Province in South China. He obtained his Bachelor of Engineer degree in Automation in Tsinghua University, China in 2005, where he has won the Champion of the Electronic Design Competition in 2003 and was a member of Tsinghua University Team for China CCTV Robot Contest.
From 09.2005, he worked as a research assistant in Microprocessor R&D Center (MPRC) in Peking University, one of the earliest Microprocessor research center in China. In MPRC, he was a member of the IC design group, where he participated in the logic synthesis and physical design of the System-on-Chips designed by MPRC. He has joined in three National Key Science Research Projects and became a project manager of his group in the middle of 2007. He graduated from Peking University with a Master of Science degree in Computer Architecture in 07.2008.
Currently, he is studying in Swiss Federal Institute of Technology at Lausanne (EPFL) as a PhD student in the School of Computer and Communication Science. He works in Integrated Systems Lab being advised by Prof. Giovanni De Micheli and Dr. Vasilis F. Pavlidis. His current research interests are on CAD for the physical design of 3-D ICs and the design flow of SoCs.
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Education
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M.S., Computer Architecture, Peking University, Beijing, China, 09.2005 - 07. 2008
B.E., Automation, Tsinghua University, Beijing, China, 09.2001 - 07.2005
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MISSION
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Integrated circuits and systems design.
Electronic Design Automation.
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ONGOING PROJECTS
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Clock Synchronization Issues of 3-D ICs.
Thermal Modeling for 3-D DRAM.
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MAIN PUBLICATIONS
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The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter, H. Xu, V. Pavlidis, W. Burleson, and G. De Micheli, International Symposium on Quality Electronic Design (ISQED), 2012, accepted
Effect of Process Variations in 3-D Global Clock Distribution Networks , H. Xu,
V. Pavlidis,
G. De Micheli, ACM Journal on Emerging Technologies in Computing Systems, accepted
Skew Variability in 3-D ICs with Multiple Clock Domains, H. Xu, V. F. Pavlidis, and G. De Micheli, Proceedings of the IEEE International Symposium on Circuits and Systems, pp.2221-2224, May 2011
Analytical Heat Transfer Model for Thermal Through-Silicon Vias, H. Xu, V. F. Pavlidis, and G. De Micheli, Proceedings of Design, Automation and Test in Europe Conference, March, 2011
Synchronization and Power Integrity Issues in 3-D ICs, V. Pavlidis, H. Xu, I. Tsioutsios, and G. De Micheli, Proceedings of Asia Pacific Conference on Circuits and Systems, pp. 536-539, 2010
Process-Induced Skew Variation for Scaled 2-D and
3-D ICs, Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli, Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect prediction, pp. 17-24, June, 2010
Repeater Insertion Techniques for 3-D Interconnects, H. Xu, V. Pavlidis, and G. De Micheli, Electronic Workshop Digest of DATE 2010 Workshop on 3D Integration, pp. 41-44, March, 2010
Repeater Insertion for Two-Terminal Nets in 3-D ICs, H. Xu, V. Pavlidis, G. De Micheli, 4th International ICST Conference on Nano-Networks, pp. 141-150, Oct., 2009
Prescribed Skew Clock Routing Algorithm with Local Topology Optimization, L. Duan, H. Xu, K. Wang, X. Cheng, Chinese Journal of Computer-Aided Design & Computer Graphics, Vol.20, No.4, pp. 452-458, 2008
A Fast Incremental Clock Skew Scheduling Algorithm for Slack Optimization, K. Wang, H. Fang, H. Xu, X. Cheng, Proceedings of Asia and South Pacific Design Automation Conference, pp. 492-497, 2008
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PRESENTATIONS
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"Modeling Issues for Thermal TSVs," Invited Talk in Design for 3D Silicon Integration Workshop (D43D), June 2011, MINATEC, Grenoble, France.
"Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter," Poster in Intel European Research&Innovation Conference, October 2011, Leixlip, Ireland.
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PROJECT EXPERIENCE
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-- SK-M project --
Design of an SoC with 24 main function modules.
Microprocessor R&D Center in Peking University, Beijing, China, 04.2007 – 06.2008.
Project Manager of IC group.
Organized the entire IC implementation of SoC.
Optimized the timing of CPU Floating Point Unit and clock structure of SoC.
Established the Multi-Voltage synthesis flow for CPU.
-- PKUnityX86 project --
Design of an X86 CPU based on Geode GX2 transferred by AMD.
Microprocessor R&D Center in Peking University, Beijing, China, 10.2006 – 01.2007.
Established semi-custom flow for X86 architecture.
Optimized the clock structure.
Evaluated different types of memory used in CPU.
-- PKUnity863II Case8 project --
Design of the MPRC UniCore II CPU, 600MHz.
Microprocessor R&D Center in Peking University, Beijing, China, 02.2006 – 08.2006.
Accomplished the physical implementation of the CPU.
Established the Multi-Voltage-Threshold flow for UniCore II.
-- The 4th Asia-Pacific Robot Contest China --
Tsinghua Univ. Team for 4th Asia-Pacific Robot Contest China, Beijing, China, 02.2005 – 08.2005.
C programming for the control systems of robots.
Designed the mechanism of automatic robots.
-- Summer Internship in SHENZHEN YOKI CO., LTD. --
SHENZHEN YOKI CO., LTD., Shenzhen, China, 07.2004 – 08.2004.
Group Leader of Summer Interns.
Accomplished PLC programming for Can Sealing Machine, enhancing the efficiency by 3 times.
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