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Panagiotis Athanasopoulos
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Name: Takis
birth date: 19.05.1982
nationality: Grec
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office(s):
ELD334
phone(s): [+41 21 69] 36931
private phone: Mobile: [+41] 787836351 Home: [+41] 216243438
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BIOGRAPHY
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Panagiotis Athanasopoulos received the equivalent of Bachelor and Master degree from Department of Computer and Communication Engineering of University of Thessaly in Greece and joined École Polytechnique Fédérale de Lausanne (EPFL) as a research assistant in the Processor Architecture Laboratory (2007-2010) and Microelectronic Systems Laboratory (2007-now) where he is currently persuing a Phd Degree in Microsystems and Microelectronics. His research interests include High-Level-Synthesis, Software Hardware Co-design, Embedded processor design and customization, 3D VLSI and FPGAs.
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Publication List
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Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici: Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. VLSI-SoC 2010: 149-154
Parandeh-Afshar, H.; Cevrero, A.; Athanasopoulos, P.; Brisk, P.; Leblebici, Y.; Ienne, P.; , "A flexible DSP block to enhance FPGA arithmetic performance," Field-Programmable Technology, 2009. FPT 2009. International Conference on , vol., no., pp.70-77, 9-11 Dec. 2009 doi: 10.1109/FPT.2009.5377638
Athanasopoulos, P., Brisk, P., Leblebici, Y., and Ienne, P. 2009. Memory organization and data layout for instruction set extensions with architecturally visible storage. In Proceedings of the 2009 international Conference on Computer-Aided Design (San Jose, California, November 02 - 05, 2009). ICCAD '09. ACM, New York, NY, 689-696. DOI= http://doi.acm.org/10.1145/1687399.1687527
Cevrero, A.; Athanasopoulos, P.; Parandeh-Afshar, H.; Skerlj, M.; Brisk, P.; Leblebici, Y.; Ienne, P.; , "Using 3D integration technology to realize multi-context FPGAs," Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on , vol., no., pp.507-510, Aug. 31 2009-Sept. 2 2009. doi: 10.1109/FPL.2009.5272454
Cevrero, A., Athanasopoulos, P., Parandeh-Afshar, H., Brisk, P., Leblebici, Y., Ienne, P., and Skerlj, M. 2009. 3D configuration caching for 2D FPGAs. In Proceeding of the ACM/SIGDA international Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 22 - 24, 2009). FPGA '09. ACM, New York, NY, 286-286. DOI= http://doi.acm.org/10.1145/1508128.1508205
Cevrero, A., Athanasopoulos, P., Parandeh-Afshar, H., Verma, A., Niaki, H., Nicopoulos, C., Gurkaynak, F., Brisk, P., Leblebici, Y., and Ienne, P. 2009. Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2, 2 (Jun. 2009), 1-36. DOI= http://doi.acm.org/10.1145/1534916.1534923
Cevrero, A., Athanasopoulos, P., Parandeh-Afshar, H., Verma, A. K., Brisk, P., Gurkaynak, F. K., Leblebici, Y., and Ienne, P. 2008. Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. In Proceedings of the 16th international ACM/SIGDA Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 24 - 26, 2008). FPGA '08. ACM, New York, NY, 181-190. DOI= http://doi.acm.org/10.1145/1344671.1344699
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| Contact |
Vcard
--Messenger--
panathanforth-at-hotmail.com
--Gmail--
panathanforth-at-gmail.com
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| Adresses |
--Personal--
Avenue De France 9
CH-1004 Lausanne
--Office--
EPFL/STI-IEL-LSM
Office ELD 333
Bldg ELD, Station 11
CH-1015 Lausanne
Switzerland
Phone: [+41 21 69] 36937
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Doctoral Assistant