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Paolo Ienne
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Processor Architecture Laboratory
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Associate Professor
PhD (EPFL, 1996)
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office(s):
INF137
phone(s): [+41 21 69] 32625,32641
fax: [+41 21 69] 95263
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BIOGRAPHY
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Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, from 1990 to 1991, he was an undergraduate researcher with Brunel University, Uxbridge, U.K. From 1992 to 1996, he was a Research Assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Center for Neuro-Mimetic Systems of the EPFL. In December 1996, he joined the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG). After working on datapath generation tools, he became Head of the embedded memory unit in the Design Libraries division.
His research interests include various aspects of computer and processor architecture, electronic design automation, computer arithmetic, reconfigurable computing, and multiprocessor systems-on-chip.
Dr. Ienne was a recipient of Best Paper Award at the 40th Design Automation Conference (DAC) in 2003, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) in 2007, and at the 19th International Conference on Field-Programmable Logic and Applications (FPL) in 2009. In 2008, he has been General Co-Chair of the 6th IEEE Symposium on Application Specific Processors (SASP) and Guest Editor of a Special Section on Application Specific Processors which appeared in October 2008 on the IEEE Transactions on Very Large Scale Integration Systems. In 2010, he is a Topic Co-Chair of Design Automation and Test in Europe (DATE) for the Architectural and High-Level Synthesis topic and the Program Subcommittee Chair of the Design Automation Conference (DAC) on High-Level and Logic Synthesis. In 2011, he will be a Program Co-Chair of the 20th IEEE Symposium on Computer Arithmetic (ARITH). He is or has been a member of the program committees of several international workshops and conferences, including Design Automation and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), the International Symposium on High-Performance Computer Architecture (HPCA), the ACM International Conference on Supercomputing (ICS), the International Conference on Field Programmable Logic and Applications (FPL), and the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).
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MAIN PUBLICATIONS
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Frédéric Worm, Paolo Ienne, Patrick Thiran, and Giovanni De Micheli.
A Robust Self-calibrating Transmission Scheme for On-chip
Networks.
IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, VLSI-13(1):126-39, 2005.
[ Details |
Full Text ]
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Miljan Vuleti, Laura Pozzi, and Paolo Ienne.
Seamless Hardware-Software Integration in Reconfigurable
Computing Systems.
IEEE Design and Test of Computers, 22(2):102-13, 2005.
[ Details |
Full Text ]
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Ajay K. Verma, Philip Brisk, and Paolo Ienne.
Progressive decomposition: A heuristic to structure arithmetic
circuits.
In Proceedings of the 44th Design Automation Conference,
pages 404-409, San Diego, Calif., 2007.
[ Details |
Full Text ]
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Laura Pozzi, Kubilay Atasu, and Paolo Ienne.
Exact and Approximate Algorithms for the Extension of
Embedded Processor Instruction Sets.
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 25(7):1209-1229, 2006.
[ Details |
Full Text |
Link ]
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Paolo Ienne and Rainer Leupers.
Customizable Embedded Processors-Design Technologies
and Applications.
Systems on Silicon Series. Morgan Kaufmann, San Mateo, Calif., 2006.
[ Details ]
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OTHER PUBLICATIONS
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Available here
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CURRENT WORK
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Configurable Datapaths.
Design Methodologies for Arithmetic Circuits.
Customizable Processors.
Ultra Low-Power Processor Architecture.
Virtual Shared-Memory for Multiprocessors on Chip.
Paolo Ienne's research is sponsored by the Swiss National Science Foundation.
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Associate Professor 