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Paolo Ienne
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Processor Architecture Laboratory
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Associate Professor
PhD (EPFL, 1996)
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office(s):
INF137
phone(s): [+41 21 69] 32625,32641
fax: [+41 21 69] 95263
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BIOGRAPHY
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Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, from 1990 to 1991, he was an undergraduate researcher with Brunel University, Uxbridge, U.K. From 1992 to 1996, he was a Research Assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Center for Neuro-Mimetic Systems of the EPFL. In December 1996, he joined the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG). After working on datapath generation tools, he became Head of the embedded memory unit in the Design Libraries division.
His research interests include various aspects of computer and processor architecture, electronic design automation, computer arithmetic, reconfigurable computing, and multiprocessor systems-on-chip.
Dr. Ienne was a recipient of Best Paper Award at the 40th Design Automation Conference (DAC) in 2003, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) in 2007, and at the 19th International Conference on Field-Programmable Logic and Applications (FPL) in 2009. In 2008, he has been General Co-Chair of the 6th IEEE Symposium on Application Specific Processors (SASP) and Guest Editor of a Special Section on Application Specific Processors which appeared in October 2008 on the IEEE Transactions on Very Large Scale Integration Systems. In 2010, he has been the Program Subcommittee Chair of the Design Automation Conference (DAC) on High-Level and Logic Synthesis. Since 2010, he is a Topic Co-Chair of Design Automation and Test in Europe (DATE) for Architectural and High-Level Synthesis topic. In 2011, he was a Program Co-Chair of the 20th IEEE Symposium on Computer Arithmetic (ARITH) and a Program Co-Chair of the 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). He is or has been a member of some fifty program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. Since 2011, he is an associate editor of ACM Transactions on Design Automation of Electronic Systems (TODAES).
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MAIN PUBLICATIONS
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Exploiting fast carry-chains of FPGAs for designing compressor trees. , Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne. , In Proceedings of the 19th International Conference on Field-Programmable Logic and Applications, pages 242-49, Prague, August 2009. Best Paper Award.
Iterative Layering: Optimizing arithmetic circuits by structuring the information flow. , Ajay K. Verma, Philip Brisk, and Paolo Ienne. , In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2009.
Virtual Ways: Efficient coherence for architecturally visible storage in automatic instruction set extensions. , Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, and Paolo Ienne. , In High Performance Embedded Architectures and Compilers, volume 5952 of Lecture Notes in Computer Science, pages 126-40. Springer, 2010. Best Paper Award Nominee.
Field programmable compressor trees: Acceleration of multi-input addition on FPGAs., Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Chrysostomos Nicopoulos, Seyed Hosein Attarzadeh Niaki, Frank K. Gurkaynak, Yusuf Leblebici, and Paolo Ienne., ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2(2):13:1-13:36, June 2009.
Fast, nearly-optimal ISE identification with I/O serialisation through maximal clique enumeration. , Ajay K. Verma, Philip Brisk, and Paolo Ienne. , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-29(3):341-54, March 2010.
Exact and approximate algorithms for the extension of embedded processor instruction sets. , Laura Pozzi, Kubilay Atasu, and Paolo Ienne. , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1209-29, July 2006.
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OTHER PUBLICATIONS
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Available here
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CURRENT WORK
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Configurable Datapaths.
Design Methodologies for Arithmetic Circuits.
Customizable Processors.
Ultra Low-Power Processor Architecture.
Virtual Shared-Memory for Multiprocessors on Chip.
Paolo Ienne's research is sponsored by the Swiss National Science Foundation.
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| Skills |
VLSI design methodologies, Processor architecture, Computer engineering
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| Teaching |
Computer Science
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| Phd programs |
- Computer, Communication and Information Sciences
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| Phd Students |
Bayrak Ali Galip
Cevrero Alessandro
George Nithin
Jimenez Xavier
Parandeh Afshar Hadi
Past Phd students:
Kluter Ties Jan Henderikus
Verma Ajay Kumar
Vuletic Miljan
Worm Frédéric
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| CONTACT |
Secretariat
Chantal Schneeberger
Building INF136
Station 14
CH-1015 Lausanne
Tel. + 41 21 693 26 41
chantal.schneeberger@epfl.ch
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