Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne. Prior to my PhD, I have received a MSc (2015) and a BSc (2013) in Electrical Engineering and Information Technology from the University of Zagreb.
 
My research focuses on methods to enable easy and efficient generation of good-quality hardware designs from high-level programming languages (e.g., C/C++). I developed an high-level synthesis (HLS) technique which is fundamentally different from the solutions described in the literature and available on the market; it produces good-quality circuits out-of-the-box and achieves behaviors that are beyond the capabilities of standard HLS tools. My work combines expertise in compilers and digital hardware design with ideas from computer architecture and particular mathematical modeling techniques. My vision for the future is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices which enable software developers from different domains to accelerate emerging compute-intensive applications.

My HLS compiler and all related documentation are available at http://dynamatic.epfl.ch/