Lana Josipovic
EPFL IC IINFCOM LAP
INF 137 (Bâtiment INF)
Station 14
CH-1015 Lausanne
Biography
Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne.
My research focuses on bridging the gap between software and hardware with the purpose of building efficient circuits for Field Programmable Gate Arrays (FPGAs). I develop new high-level synthesis (HLS) techniques: the purpose is to generate hardware designs from high-level programming languages and to enable software developers to build efficient accelerators. I aim to change the HLS paradigm so that the produced circuits share key features with modern superscalar processors and are able to handle important classes of irregular and control-dominated applications.
I am grateful to have received the Google PhD Fellowship, the EPFL EDIC Fellowship, and the Google Anita Borg (Women Techmakers) Scholarship.
Publications
Autres publications
| Lana Josipović, Radhika Ghosal, and Paolo Ienne. Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2018. Best Paper Award Nominee. |
In Dynamically scheduled high-level synthesis. |
| Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, Korea, October 2017. Best Paper Award Nominee. |
An out-of-order load-store queue for spatial computing. |
| Lana Josipović, Philip Brisk, and Paolo Ienne In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, Calif., October 2017. |
From C to elastic circuits. |
| Lana Josipović, Philip Brisk, and Paolo Ienne. ACM Transactions on Embedded Computing Systems (TECS), 16(5s):125:1–125:19, September 2017. |
An out-of-order load-store queue for spatial computing. |
| Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, Calif., April 2017. |
An out-of-order load-store queue for spatial computing. |
| Lana Josipović, Nithin George, and Paolo Ienne. In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 177–80, Xi'an, China, December 2016. |
Enriching C-based high-level synthesis with parallel pattern templates. |
Publications
- Dynamically scheduled high-level synthesis. Lana Josipović, Radhika Ghosal, and Paolo Ienne. In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 127–136, Monterey, Calif., February 2018. Best Paper Award Nominee.
- An out-of-order load-store queue for spatial computing. Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, Korea, October 2017. Best Paper Award Nominee.
- From C to elastic circuits. Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121–125, Pacific Grove, Calif., October 2017.
- An out-of-order load-store queue for spatial computing. Lana Josipović, Philip Brisk, and Paolo Ienne. ACM Transactions on Embedded Computing Systems (TECS), 16(5s):125:1–125:19, September 2017.
- An out-of-order load-store queue for spatial computing. Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines, page 134, Napa, Calif., April 2017.
- Enriching C-based high-level synthesis with parallel pattern templates. Lana Josipović, Nithin George, and Paolo Ienne. In Proceedings of the IEEE International Conference on Field Programmable Technology, pages 177–80, Xi'an, China, December 2016.