Lana Josipovic
EPFL IC IINFCOM LAP
INF 137 (Bâtiment INF)
Station 14
CH-1015 Lausanne
Web site: Web site: https://lap.epfl.ch/
Web site: Web site: https://go.epfl.ch/edic_program
Biography
Hi! I am Lana, a doctoral student in the Processor Architecture Laboratory led by Professor Paolo Ienne. Prior to my PhD, I have received a MSc (2015) and a BSc (2013) in Electrical Engineering and Information Technology from the University of Zagreb.
My research focuses on methods to enable easy and efficient generation of good-quality hardware designs from high-level programming languages (e.g., C/C++). I developed an high-level synthesis (HLS) technique which is fundamentally different from the solutions described in the literature and available on the market; it produces good-quality circuits out-of-the-box and achieves behaviors that are beyond the capabilities of standard HLS tools. My work combines expertise in compilers and digital hardware design with ideas from computer architecture and particular mathematical modeling techniques. My vision for the future is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices which enable software developers from different domains to accelerate emerging compute-intensive applications.
My HLS compiler and all related documentation are available at http://dynamatic.epfl.ch/
My research focuses on methods to enable easy and efficient generation of good-quality hardware designs from high-level programming languages (e.g., C/C++). I developed an high-level synthesis (HLS) technique which is fundamentally different from the solutions described in the literature and available on the market; it produces good-quality circuits out-of-the-box and achieves behaviors that are beyond the capabilities of standard HLS tools. My work combines expertise in compilers and digital hardware design with ideas from computer architecture and particular mathematical modeling techniques. My vision for the future is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices which enable software developers from different domains to accelerate emerging compute-intensive applications.
My HLS compiler and all related documentation are available at http://dynamatic.epfl.ch/
Awards
Best Paper Award at FPGA'20
2020
Google PhD Fellowship for Systems and Networking
2018
Best Paper Award Nominee at FPGA'18
2018
Best Paper Award Nominee at CASES'17
2017
EPFL EDIC Doctoral Fellowship
2015
Google Anita Borg (Women Techmakers) Scholarship
2015
Publications
Selected publications
Lana Josipović, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 186–96, Seaside, Calif., February 2020. |
Buffer placement and sizing for high-performance dataflow circuits. Best Paper Award. |
Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne, and John Wickerson. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 288–98, Seaside, Calif., February 2020. |
Combining dynamic & static scheduling in high-level synthesis. |
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. In Proceedings of the 28th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’20), pages 1–10, Seaside, Calif., February 2020. |
Dynamatic: From C/C++ to dynamically scheduled circuits. |
Lana Josipović, Atri Bhattacharyya, Andrea Guerrieri, and Paolo Ienne. In Proceedings of the IEEE Intl. Conference on Field Programmable Technology (FPT’19), pages 197–205, Tianjin, China, December 2019. |
Shrink it or shed it! Minimize the use of LSQs in dataflow designs. |
Lana Josipović, Andrea Guerrieri, and Paolo Ienne. In Proceedings of the 27th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’19), Monterey, Calif., February 2019. |
Speculative dataflow circuits |
Lana Josipović, Radhika Ghosal, and Paolo Ienne. In Proceedings of the 26th ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays (FPGA’18), pages 127-36, Monterey, Calif., February 2018. |
Dynamically scheduled high-level synthesis. Best Paper Award Nominee. |
Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the Intl. Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES’17), Seoul, Korea, October 2017. |
An out-of-order load-store queue for spatial computing. Best Paper Award Nominee. See ACM TECS paper below. |
Lana Josipović, Philip Brisk, and Paolo Ienne. ACM Transactions on Embedded Computing Systems (TECS'17), 16(5s):125:1–125:19, September 2017. |
An out-of-order load-store queue for spatial computing. |
Lana Josipović, Philip Brisk, and Paolo Ienne In Proceedings of the 51st Annual Asilomar Conference on Signals, Systems, and Computers, pages 121-25, Pacific Grove, Calif., October 2017. |
From C to elastic circuits. |
Lana Josipović, Philip Brisk, and Paolo Ienne. In Proceedings of the 25th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’17), page 134, Napa, Calif., April 2017. |
An out-of-order load-store queue for spatial computing. |
Lana Josipović, Nithin George, and Paolo Ienne. In Proceedings of the 26th IEEE Intl. Conference on Field Programmable Technology (FPT’16), pages 177–80, Xi'an, China, December 2016. |
Enriching C-based high-level synthesis with parallel pattern templates. |