Arnout was born in Leuven, Belgium. He received the M.Sc. degree in Nanoelectronics from KU Leuven in 2016. He wrote his M.Sc. thesis in the Physics Modeling and Simulation group at imec, Leuven, on the simulation of energy filtering in superlattice-based nanowires. In October 2016, he joined ICLAB as part of the European H2020 MOS-Quito Project (MOS-based Quantum Information Technology) to model the MOS transistor at cryogenic temperatures, dedicated to the design of cryogenic analog-RF circuits for improved qubit control. His research interests include quantum technology, low-temperature electronics, quantum physics, and cryogenic experiments.
Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors
Journal Of Applied Physics. 2018-10-14.
DOI : 10.1063/1.5043543.
Cryogenic MOS Transistor Model
IEEE Transactions on Electron Devices. 2018-08-01.
DOI : 10.1109/TED.2018.2854701.
Characterization and Modeling of 28 nm Bulk CMOS Technology down to Cryogenic Temperatures (4.2 K)
IEEE Journal of the Electron Devices Society. 2018-03-27.
DOI : 10.1109/JEDS.2018.2817458.
28-nm Bulk and FDSOI Cryogenic MOSFET (Invited Paper)
2018-01-01. IEEE International Conference on Integrated Circuits, Technologies and Applications (IEEE ICTA) , Beijing, PEOPLES R CHINA , Nov 21-23, 2018. p. 45-46.
Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures
Solid-State Electronics. 2018.
DOI : 10.1016/j.sse.2019.03.033.
Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing
2018. EUROSOI-ULIS 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon , Granada, Spain , March 19–21, 2018.
Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing
2017. Solid-State Device Research Conference (ESSDERC), 2017 47th European , Leuven, Belgium, , 11-14 Sept. 2017.
DOI : 10.1109/ESSDERC.2017.8066592.