Paul Victor Georges Muller
Paul received his M.Sc. and Dr. Sc. degrees in Electrical Engineering from the Ecole Polytechnique Fédérale de Lausanne (EPFL) in 1999 and 2006 respectively. From 1999 to 2002, he worked as an analog and mixed-signal design engineer on low-power sensing and data acquisition circuits at XEMICS (now part of Semtech Corp.). From 2002 to 2006, he worked as a research assistant and doctoral student on the design and modeling of multi-channel gigabit receivers for short-distance optical communication interfaces. From 2006 to 2009, he has been with Marvell Semiconductor working on wireless circuits for connectivity combo ICs. In 2010, he joined the cellular RF team of Mediatek in the UK and contributed to several generations of 3G/3.75G and 4G transceivers as an RFIC designer and design team leader. Since 2015, he is the RFID Business Unit Technical Leader at EM Microelectronic, responsible for day-to-day supervision of all RFID-related activities from LF (125kHz) to UHF (900MHz) transponders as well as car access solutions.
Since 2016, Paul is lecturing part-time at his former Alma Mater EPFL.
Paul's research interests are in the area of advanced analog and RF IC circuits, top-down system-level budgeting and design and top-level verification of complex SoCs.
RF/Analog IC Design
Wireless Transceiver Systems and Circuits
High-Speed Data Communication Circuits
Low-Power Low-Voltage Design
High-Speed and RF Test & Measurement
|P.Muller, A.Tajalli, M.Atarodi, Y.Leblebici
Proceedings of Design, Automation and Test in Europe, Munich, Germany, March 2005
|Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit|
|P.Muller, Y.Leblebici, M.K.Emsley, M.S.Unlu
Proceedings of the 34th European Solid-State Circuits Conference, Leuven, Belgium, September 2004
|A 4-channel 2.5Gb/s/channel 66dBOhm Inductorless Transimpedance Amplifier|
P. Muller; M. K. Emsley; A. Tajalli; M. Ataraodi; M. S. Unlü et al. : Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links. 2006. 32nd European Solid-State Circuits Conference (ESSCIRC), Montreux, Switzerland, September 18-22. p. 480-483. DOI : 10.1109/ESSCIR.2006.307494.
P. Muller / Y. Leblebici (Dir.) : A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications. Lausanne, EPFL, 2006. DOI : 10.5075/epfl-thesis-3600.
P. Muller; A. Tajalli; M. Atarodi; Y. Leblebici : Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. 2005. Design, Automation and Test in Europe (DATE), Munich, Germany, March 7-11. p. 258 - 263. DOI : 10.1109/DATE.2005.315.
P. Muller; Y. Leblebici : Limiting Amplifiers for Next-Generation Multi-Channel Optical I/O Interfaces in SoCs. 2005. IEEE International SOC Conference, Herndon, Virginia, USA, September 25-28.
P. Muller; Y. Leblebici : Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS. 2005. Forum on Specification and Design Languages (FDL), Lausanne, Switzerland, September 27-30.
P. Muller; Y. Leblebici; M. K. Emsley; M. S. Ünlü : A 4-channel 2.5Gb/s/channel 66dBOhm Inductorless Transimpedance Amplifier. 2004. 34th European Solid-State Circuits Conference, Leuven, Belgium, September 2004.