Seyed Armin Tajalli

Edit profile

seyed.tajalli@epfl.ch +41 21 693 78 88

+41 21 693 78 88
EPFL > STI > IEM > INL

Web site: Web site: https://www.epfl.ch/labs/inl/

vCard
Administrative data

Fields of expertise

-Ultra Low Power Circuits -Analog/Mixed-Signal Circuits -Data Converters -Serial Data Transceivers -Clock and Data Recovery -Phase-locked loop -Frequency synthesizer -RFID -RF/high-frequency circuits

Mission

My work has been mainly focused on design and implementation of high-performance and low-power integrated circuits. Developing design techniques for implementing ultra-low power integrated systems, reconfigurable analog circuits, very high-speed circuit for telecommunication systems, and dynamic power-speed control are some of the main topics that recently I have been working on.

Biography

Armin Tajalli received the B.S.E.E. and M.S.E.E degrees (with honors) from Sharif University of Technology, Tehran, and Tehran Polytechnic University in 1997, and 1999, respectively. He has received his Ph.D.E.E. on low-power integrated circuit design techniques in 2010 from Swiss Federal Institute of Technology (EPFL). He was with Emad Semicon during 1998-2006 as a senior analog/RF design engineer and technical manager. From 2006 he has joined Microelectronic Systems Laboratory (LSM) in Swiss Federal Institute of Technology in Lausanne (EPFL) working on design of ultra-low power circuits, high speed serial links, and circuits for RFID systems. From 2010 he has been with ALGO team developing architectures and circuits for very high-speed and very power-efficient serial data transceivers (Kandou signaling method). He has received the Kharazmi Award on Research and Development, 2000, Outstanding Design Engineer, Emad Semicon, 2001, Presidential Award of the best Iranian researchers, 2003, ACM/CICC Award, 2009, and EPFL Prime Special Award, 2009. He has served as a technical program committee member in IEEE International Conference on Computer Design (ICCD), 2010 and 2012, and VLSI-SoC, 2012.

Mailing Address

EPFL STI IEL LSM ELD 335 (Bâtiment EL) Station 11 CH-1015 Lausanne Switzerland

Contact

ph 41 21 693 1316 fx 41 21 693 6959

Publications

Infoscience publications

Infoscience

Low Noise Clock Generation: Modeling, Analysis and Implementation

D. Kostak / Y. Leblebici; A. P. Burg (Dir.)

Lausanne, EPFL, 2021. DOI : 10.5075/epfl-thesis-8454.

Seyed Armin Tajalli

Fields of expertise

Mission

Biography

Mailing Address

Contact

Publications

Infoscience publications

Infoscience

Low Noise Clock Generation: Modeling, Analysis and Implementation

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI

High-Speed ADC Design and Optimization for Wireline Links

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

A Versatile Spectrum Shaping Scheme for Communicating Beyond Notches in Multi-Drop Interfaces

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

A 4×9 Gb/s 1 pJ/b Hybrid NRZ/Multi-Tone I/O with Crosstalk and ISI Reduction for Dense Interconnects

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

A 40-nm Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

A 5.43-μW 0.8-V Subthreshold Current-Sensing Σ∆ Modulator for Low-Noise Sensor Interfaces

Efficient processing and detection of balanced codes

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Subthreshold Source-Coupled Logic

Power and Area Efficient MOSFET-C Filter for Very Low Frequency Applications

Design trade-offs in ultra-low-power CMOS and STSCL digital systems

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

An area and power optimization technique for CMOS bandgap voltage references

Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Ultra-Low Power 32-bit Pipelined Adder Using Subthreshold Source-Coupled Logic with 5fJ/stage PDP

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Improving the power-delay performance in subthreshold source-coupled logic circuits

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

Pico-Watt Source-Coupled Logic Circuits

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Implementing Ultra-high-Value Floating Tunable CMOS Resistors

Wide tuning range linearity improved biquadratic transconductor-C filter

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Low Noise Clock Generation: Modeling, Analysis and Implementation

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI

High-Speed ADC Design and Optimization for Wireline Links

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics