Siang-Yun Lee
Biography
Siang-Yun Lee is a Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli.She graduated from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis.
Her research interests include logic synthesis and computational neuroscience.
Fields of interest
- Electronic Design Automation -- Logic Synthesis
- Computational Neuroscience
Education
Bachelor
Electrical Engineering
National Taiwan University
2015-2019
Publications
Selected publications
| Siang-Yun Lee, Nian-Ze Lee and Jie-Hong R. Jiang ICCAD'18 |
Canonicalization of Threshold Logic Representation and Its Applications |
| Siang-Yun Lee, Nian-Ze Lee and Jie-Hong R. Jiang ICCAD'19 |
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks |