Stefan Nikolic
Biography
Hi! I am Stefan, a doctoral student in the Processor Architecture Laboratory, advised by Professor Paolo Ienne. Prior to my PhD, I have received a BSc (2017) in Electrical and Computer Engineering from the University of Novi Sad.I am broadly interested in FPGA architecture and CAD. In particular, my research focuses on developing new methods for efficiently exploring the design space of FPGA interconnect architecture. Although many of problems in this area have been considered almost closed in the past two decades, surging resistance of lower metal layers driven by technology scaling rendered most of the long standing rules of thumb used in interconnect architecture design obsolete. My goal is to combine state-of-the-art modeling with search methods based on combinatorial optimization, leveraging the specificities of the place and route algorithms, and clever heuristics, to rethink FPGA interconnect architecture in this new context. Novel architectures sometimes require new CAD algorithms which has allowed me to be active on that front as well.
Between September 2021 and February 2022, I interned in the Architecture team of Xilinx (now AMD), working on similar problems with Chirag Ravishankar and Dinesh Gaitonde.
Awards
Michal Servit Best Paper Award at FPL'21
2021
Michal Servit Best Paper Award at FPL'20
2020
EPFL EDIC Doctoral Fellowship
2017
Publications
Selected publications
Stefan Nikolić, Grace Zgheib, Paolo Ienne ACM Transactions on Reconfigurable Technology and Systems |
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. To Appear |
Stefan Nikolić and Paolo Ienne In Proceedings of the 31st International Conference on Field‐Programmable Logic and Applications, Dresden, Germany (virtual), August 2021. Best Paper Award. |
Turning PathFinder Upside‐Down: Exploring FPGA Switch‐Blocks by Negotiating Switch Presence. Best Paper Award |
Stefan Nikolić, Francky Catthoor, Zsolt Tőkei, and Paolo Ienne In Proceedings of the 29th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 34–44, Seaside, Calif. (virtual), February 2021. |
Global is the New Local: FPGA Architecture at 5 nm and Beyond |
Morten B. Petersen, Stefan Nikolić, Mirjana Stojilović In Proceedings of the 29th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 11–22, Seaside, Calif. (virtual), February 2021. |
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs |
Stefan Nikolić, Grace Zgheib, and Paolo Ienne In Proceedings of the 30th International Conference on Field‐Programmable Logic and Applications, pages 153–61, Gothenburg, Sweden (virtual), August 2020. |
Timing‐Driven Placement for FPGA Architectures with Dedicated Routing Paths. Best Paper Award |
Stefan Nikolić, Grace Zgheib, and Paolo Ienne In Proceedings of the 28th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 150–60, Seaside, Calif., February 2020. |
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing |
Stefan Nikolić, Grace Zgheib, and Paolo Ienne In Proceedings of the 29th International Conference on Field-Programmable Logic and Applications, pages 31–37, Barcelona, Spain, September 2019. |
Finding a Needle in the Haystack of Hardened Interconnect Patterns |