Biography

Yusuf Leblebici received his B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, in 1984 and in 1986, respectively, and his Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University.

Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis.

He is the coauthor of 4 textbooks, namely, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition 1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Springer, 2007) and Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge University Press, 2009), as well as more than 300 articles published in various journals and conferences.

He has served as an Associate Editor of IEEE Transactions on Circuits and Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE and has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.

MAIN PUBLICATIONS

A. Tajalli and Y. Leblebici. Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Transaction on Circuits and Systems-II, 56(5):347-351, 2009.

A. Tajalli and Y. Leblebici. A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology. IEEE Journal of Solid-State Circuits, 44(2):538-548, 2009.

A. Tajalli, M. Alioto, and Y. Leblebici. Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits. IEEE Transaction on Circuits and Systems-II, 56(2):127-131, 2009.

M. Stanisavljevic, A. Schmid, and L. Leblebici. Optimization of the Averaging Reliability Technique using Low Redundancy Factors for Nanoscale Technologies. IEEE Transactions on Nanotechnology, 8(2), 2009.

N. Joye, A. Schmid, and Y. Leblebici. Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays. Neurocomputing, 73:250-259, 2009.

H. Ben Jamaa, B. K. Boroujeni, G. de Micheli, Y. Leblebici, C. Piguet, A. Schmid, and M. Stanisavljevic. Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS. In Nanosystems Design and Technology, volume Chapter 3, pages 45-84. Springer, 2009.

M. H. Ben Jamaa, K. E. Moselund, D. Atienza, D. Bouvet, A. M. Ionescu, Y. Leblebici, and G. De Micheli. Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(11):2053-2067, 2008.

M. Stanisavljevic, A. Schmid, and Y. Leblebici. Optimization of nanoelectronic systems' reliability under massive defect density using Cascaded R-fold modular redundancy. Nanotechnology, 19, 2008.

K. E. Moselund, D. Bouvet, M. H. Ben Jamaa, D. Atienza, Y. Leblebici, G. De Micheli, and M. A. Ionescu. Prospects for logic-on-a-wire. Microelectronic Engineering, 85(5-6):1406-1409, 2008.

A. Tajalli, E. J. Brauer, Y. Leblebici, and E. Vittoz. Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications. IEEE Journal of Solid-State Circuits, 43(7):1699 - 1710, 2008.

A. Tajalli, P. Muller, and Y. Leblebici. A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE Journal of Solid-State Circuits, 42(10):2235-2244, 2007.

Z. Toprak-Deniz, Y. Leblebici, and E. Vittoz. On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. IEEE Journal of Solid-State Circuits, 42(7):1593-1606, 2007.