Paolo Ienne has been a professor in the School of Computer and Communication Sciences at EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Before joining EPFL, he worked at Siemens Semiconductors, later Infineon Technologies, in Munich, where he headed the Embedded Memories Unit in the Design Libraries Division. His research spans computer and processor architecture, FPGAs and reconfigurable computing, high-level synthesis, electronic design automation, and computer arithmetic. He has published over 200 peer-reviewed papers. His work has received best paper awards at FPGA (2012, 2016, and 2020), FPL (2009, 2020, 2021, and 2024), CASES (2007), and DAC (2003), as well as a best paper runner-up distinction at FPGA 2026 and an honourable mention at ASPLOS 2026. Dynamatic, the open-source synthesis tool developed jointly by his group and Lana Josipović's group at ETH Zurich, received the FPL Community Award in 2026. He has served as general or programme chair of conferences including ASAP, ARITH, FPL, and FPGA, notably as general co-chair of FPL 2016 in Lausanne. He chairs the FPL steering committee and serves on the steering committees of ARITH and FPGA. He has been an associate editor of ACM Computing Surveys since 2014 and previously served as an associate editor of ACM Transactions on Architecture and Code Optimization (TACO) from 2015 to 2026 and ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.