Andreas Peter Burg
EPFL STI IEL TCL
ELD 130 (Bâtiment ELD)
Station 11
1015 Lausanne
+41 21 693 69 24
+41 21 693 10 36
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Biography
Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006. In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor. In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP). Research interests and expertise * Circuits and systems for telecommunications (wireless and wired) * Prototyping and silicon implementation of new communication technologies * Development of communication algorithms and optimization for hardware implementation * Low-power VLSI signal processing for communications and other applications * Digital integrated circuits * Circuits for image and video processingPublications
Infoscience publications
Infoscience
Efficient Ordered Statistics Decoder with Unfolded Gaussian Elimination
2025. 2025 13th International Symposium on Topics in Coding, Los Angeles, CA, USA, 2025-08-18 - 2025-08-22. DOI : 10.1109/istc65386.2025.11154634.An Ultra Low Power Analog/Mixed-Signal Processor for a Smart RF Signal Classification System in the ISM Band
2025. 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, USA, 2025-06-15 - 2025-06-17. p. 259 - 262. DOI : 10.1109/rfic61188.2025.11082785.An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing
2025. 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025-05-25 - 2025-05-28. p. 1 - 5. DOI : 10.1109/iscas56072.2025.11043800.Toward Universal Belief Propagation Decoding for Short Binary Block Codes
IEEE Journal on Selected Areas in Communications. 2025. DOI : 10.1109/JSAC.2025.3536505.Edge-Spreading Raptor-Like LDPC Codes for 6G Wireless Systems
IEEE Transactions on Communications. 2025. DOI : 10.1109/tcomm.2025.3576907.Vital Signs and Human Activity Sensing with Wireless Systems
Lausanne, EPFL, 2025. DOI : 10.5075/epfl-thesis-10593.Device-Free Floor-Scale Human Detection With Indoor LTE Antennas
IEEE Open Journal of the Communications Society. 2025. DOI : 10.1109/OJCOMS.2025.3560153.Iterative Logistic Weight Based Chase Decoder for Open Forward Error Correction
2025. Optical Fiber Communication Conference (OFC) 2025, San Francisco, United States, 2025-03-30 - 2025-04-03. DOI : 10.1364/OFC.2025.Tu2F.6.Efficient Algorithms and VLSI Implementations of FEC Decoders for B5G/6G
Lausanne, EPFL, 2025. DOI : 10.5075/epfl-thesis-11443.Design, Optimization and Verification of Embedded Gain Cell RAMs
Lausanne, EPFL, 2025. DOI : 10.5075/epfl-thesis-11194.Centralized RAN for LPWAN: Architecture and Proof-of-Concept Prototype Implementation
2024. 2024 IEEE Conference on Network Function Virtualization and Software Defined Networks, Natal, Brazil, 2024-11-05 - 2024-11-07. DOI : 10.1109/NFV-SDN61811.2024.10807469.LoRa Fine Synchronization with Two-Pass Time and Frequency Offset Estimation
2024. 2024 58th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2024-10-27 - 2024-10-30. p. 1802 - 1806. DOI : 10.1109/ieeeconf60004.2024.10942846.Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes
2024. 2024 58th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2024-10-27 - 2024-10-30. p. 980 - 984. DOI : 10.1109/ieeeconf60004.2024.10942947.A High Dynamic Range Envelop Detector for Heterodyne Receiver Architecture
Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2024. DOI : 10.1109/TCSII.2023.3329038.A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation
Ieee Transactions On Circuits And Systems I-Regular Papers. 2024. DOI : 10.1109/TCSI.2024.3368056.A GRANDAB Decoder with 8.48 Gbps Worst-Case Throughput in 65nm CMOS
2024. 50 IEEE European Solid-State Electronics Research Conference, Bruges, Belgium, 2024-09-09 - 2024-09-12. p. 685 - 688. DOI : 10.1109/ESSERC62670.2024.10719587.A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time
IEEE Journal of Solid-State Circuits. 2024. DOI : 10.1109/JSSC.2024.3489793.A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support
IEEE Transactions on Circuits and Systems I: Regular Papers. 2024. DOI : 10.1109/TCSI.2024.3443598.A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving
2024. IEEE International Symposium on Circuits and Systems, Singapore, Singapore, 2024-05-19 - 2024-05-22. DOI : 10.1109/ISCAS58744.2024.10558152.Learning-based Hand Gesture Classification using Channel Impulse Response with UWB
2024. 35 IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Valencia, Spain, 2024-09-02 - 2024-09-05. DOI : 10.1109/PIMRC59610.2024.10817379.Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning
Lausanne, EPFL, 2024. DOI : 10.5075/epfl-thesis-10599.High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes
Ieee Transactions On Signal Processing. 2024. DOI : 10.1109/TSP.2024.3361073.Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi
2024. 25 IEEE Wireless Communications and Networking Conference, Dubai, United Arab Emirates, 2024-04-21 - 2024-04-24. DOI : 10.1109/WCNC57260.2024.10570912.An Ultra-Low-Power Widely-Tunable Complex Band-Pass Filter for RF Spectrum Sensing
Ieee Transactions On Circuits And Systems I-Regular Papers. 2023. DOI : 10.1109/TCSI.2023.3300965.Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN
2023. 57 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, United States, 2023-10-29 - 2023-11-01. p. 197 - 201. DOI : 10.1109/IEEECONF59524.2023.10476850.Improved Belief Propagation Decoding of Turbo Codes
2023. 48th IEEE International Conference on Acoustics, Speech and Signal Processing, Rhodes Island, Greece, 2023-06-04 - 2023-06-10. DOI : 10.1109/ICASSP49357.2023.10097058.Low Power LDPC Decoding by Reliable Voltage Down-Scaling
2023. 9th IEEE Nordic Circuits and Systems Conference (NorCAS), Aalborg, DENMARK, OCT 31-NOV 01, 2023. DOI : 10.1109/NorCAS58970.2023.10305442.Band-of-Interest-based Channel Impulse Response Fusion for Breathing Rate Estimation with UWB
2023. IEEE International Conference on Communications (IEEE ICC), Rome, ITALY, MAY 28-JUN 01, 2023. p. 1695 - 1700. DOI : 10.1109/ICCWORKSHOPS57953.2023.10283555.Spreading Factor assisted LoRa Localization with Deep Reinforcement Learning
2023. 97th IEEE Vehicular Technology Conference (VTC-Spring), Florence, ITALY, JUN 20-23, 2023. DOI : 10.1109/VTC2023-Spring57618.2023.10200189.A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI
Ieee Solid-State Circuits Letters. 2023. DOI : 10.1109/LSSC.2022.3232775.A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation
Ieee Internet Of Things Journal. 2022. DOI : 10.1109/JIOT.2022.3186732.Space Localisation
2022Design for Test With Unreliable Memories by Restoring the Beauty of Randomness
Ieee Design & Test. 2022. DOI : 10.1109/MDAT.2021.3081687.Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes
Ieee Wireless Communications Letters. 2022. DOI : 10.1109/LWC.2021.3129470.Increasing Cellular Network Energy Efficiency for Railway Corridors
2022. 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), ELECTR NETWORK, Mar 14-23, 2022. p. 1103 - 1106. DOI : 10.23919/DATE54114.2022.9774757.Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes
2022. IEEE International Conference on Communications (ICC), Seoul, SOUTH KOREA, May 16-20, 2022. p. 116 - 122. DOI : 10.1109/ICC45855.2022.9839072.Beam Selection and Tracking for Amplify-and-Forward Repeaters
2022. IEEE 95th Vehicular Technology Conference: (VTC-Spring), Helsinki, FINLAND, Jun 19-22, 2022. DOI : 10.1109/VTC2022-Spring54318.2022.9860548.List Ordered Statistics Decoders for Polar Codes
2022. 56th Asilomar Conference on Signals, Systems, and Computers, ELECTR NETWORK, Oct 31-Nov 02, 2022. p. 628 - 633. DOI : 10.1109/IEEECONF56349.2022.10051951.Cellular Fronthauling for Data Capacity Increase in Underserved Spaces
Lausanne, EPFL, 2022. DOI : 10.5075/epfl-thesis-9699.64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique
Ieee Solid-State Circuits Letters. 2022. DOI : 10.1109/LSSC.2022.3182531.A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation
Ieee Transactions On Signal Processing. 2022. DOI : 10.1109/TSP.2022.3216921.ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories
2022On the Advantage of Coherent LoRa Detection in the Presence of Interference
Ieee Internet Of Things Journal. 2021. DOI : 10.1109/JIOT.2021.3058792.An Energy-Autonomous Wireless Sensor With Simultaneous Energy Harvesting and Ambient Light Sensing
Ieee Sensors Journal. 2021. DOI : 10.1109/JSEN.2021.3068134.Adding Indoor Capacity without Fiber Backhaul: An mmWave Bridge Prototype
Ieee Communications Magazine. 2021. DOI : 10.1109/MCOM.001.2000722.Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding
Ieee Transactions On Vehicular Technology. 2021. DOI : 10.1109/TVT.2021.3052550.ComplexBeat: Breathing Rate Estimation from Complex CSI
2021. 35th IEEE Workshop on Signal Processing Systems (IEEE SiPS), Coimbra, PORTUGAL, Oct 19-21, 2021. p. 217 - 222. DOI : 10.1109/SiPS52927.2021.00046.Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers
Ieee Open Journal Of The Communications Society. 2021. DOI : 10.1109/OJCOMS.2021.3134091.A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System
2021. 19th IEEE International New Circuits and Systems Conference (NEWCAS), ELECTR NETWORK, Jun 13-16, 2021. DOI : 10.1109/NEWCAS50681.2021.9462768.Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems
2021. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Daegu, SOUTH KOREA, May 22-28, 2021. DOI : 10.1109/ISCAS51556.2021.9401331.Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System
2021. 20th IEEE Sensors Conference, ELECTR NETWORK, Oct 31-Nov 04, 2021. DOI : 10.1109/SENSORS47087.2021.9639712.Adaptive Body Biasing in Strong Body Factor Technologies
Lausanne, EPFL, 2021. DOI : 10.5075/epfl-thesis-10483.Improving Railway Track Coverage with mmWave Bridges: A Measurement Campaign
2021. 1st Workshop on 5G Measurements, Modeling, and Use Cases (5G-MeMU), ELECTR NETWORK, Aug 23, 2021. p. 8 - 13. DOI : 10.1145/3472771.3472774.Hardware Implementation of Neural Self-Interference Cancellation
Ieee Journal On Emerging And Selected Topics In Circuits And Systems. 2020. DOI : 10.1109/JETCAS.2020.2992370.Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations
Ieee Journal On Emerging And Selected Topics In Circuits And Systems. 2020. DOI : 10.1109/JETCAS.2020.2999944.Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space
Ieee Transactions On Circuits And Systems I-Regular Papers. 2020. DOI : 10.1109/TCSI.2020.2971695.Design and Decoding of Irregular LDPC Codes Based on Discrete Message Passing
Ieee Transactions On Communications. 2020. DOI : 10.1109/TCOMM.2019.2944159.Gain-Cell Embedded DRAMs: Modeling and Design Space
Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2020. DOI : 10.1109/TVLSI.2019.2955933.On the Error Rate of the LoRa Modulation With Interference
Ieee Transactions On Wireless Communications. 2020. DOI : 10.1109/TWC.2019.2952584.Identification of Non-Linear RF Systems Using Backpropagation
2020. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICCWorkshops49005.2020.9145367.GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI
2020. IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, Oct 10-21, 2020. DOI : 10.1109/ISCAS45731.2020.9180997.Lupulus: A Flexible Hardware Accelerator For Neural Networks
2020. IEEE International Conference on Acoustics, Speech, and Signal Processing, Barcelona, SPAIN, May 04-08, 2020. p. 1608 - 1612. DOI : 10.1109/ICASSP40776.2020.9054764.An Open-Source LoRa Physical Layer Prototype on GNU Radio
2020. 21st IEEE International Workshop on Signal Processing Advances in Wireless Communications (IEEE SPAWC), ELECTR NETWORK, May 26-29, 2020. DOI : 10.1109/SPAWC48557.2020.9154273.A Maximum-Likelihood-based Multi-User LoRa Receiver Implemented in GNU Radio
2020. 54th Asilomar Conference on Signals, Systems, and Computers, ELECTR NETWORK, Nov 01-05, 2020. p. 1106 - 1111. DOI : 10.1109/IEEECONF51394.2020.9443502.Complexity-efficient Fano Decoding of Polarization-adjusted Convolutional (PAC) Codes
2020. International Symposium on Information Theory and its Applications (ISITA), ELECTR NETWORK, Oct 24-27, 2020. p. 200 - 204.Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10353.Gain-Cell Embedded DRAMs: Modeling and Design Space
2020. IEEE International Symposium on Circuits and Systems (ISCAS), ELECTR NETWORK, Oct 10-21, 2020. DOI : 10.1109/ISCAS45731.2020.9180999.A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET
Ieee Solid-State Circuits Letters. 2020. DOI : 10.1109/LSSC.2020.3006496.Physical Layer Aspects of LoRa and Full-Duplex Wireless Transceivers
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10258.A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
Ieee Journal Of Solid-State Circuits. 2020. DOI : 10.1109/JSSC.2019.2938414.Training Channel Selection for Learning-based 1-bit Precoding in Massive MU-MIMO
2020. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICCWorkshops49005.2020.9145443.On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation
2020. 54th Asilomar Conference on Signals, Systems, and Computers, ELECTR NETWORK, Nov 01-05, 2020. p. 969 - 973. DOI : 10.1109/IEEECONF51394.2020.9443274.Coded LoRa Frame Error Rate Analysis
2020. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICC40277.2020.9148806.GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI
Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2019. DOI : 10.1109/TCSII.2019.2896164.2019 International Symposium on Low Power Electronics and Design
Ieee Design & Test. 2019. DOI : 10.1109/MDAT.2019.2941713.Low-Power Design of Digital VLSI Circuits around the Point of First Failure
Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9180.3.5 GHz Coverage Assessment with a 5G Testbed
2019. 89th IEEE Vehicular Technology Conference (VTC Spring), Kuala Lumpur, MALAYSIA, Apr 28-May 01, 2019. DOI : 10.1109/VTCSpring.2019.8746551.Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios
2019. 53rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Nov 03-06, 2019. p. 1149 - 1153. DOI : 10.1109/IEEECONF44664.2019.9048900.LoRa Symbol Error Rate Under Non-Aligned Interference
2019. 53rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Nov 03-06, 2019. p. 1957 - 1961. DOI : 10.1109/IEEECONF44664.2019.9048665.A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
2019. IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, Feb 17-21, 2019. p. 476 - 478. DOI : 10.1109/ISSCC.2019.8662505.JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS
2019. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 101 - 104. DOI : 10.1109/PRIME.2019.8787786.A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS
2019. 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr 14-17, 2019. DOI : 10.1109/CICC.2019.8780199.Lora Digital Receiver Analysis And Implementation
2019. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1498 - 1502. DOI : 10.1109/ICASSP.2019.8683504.A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET
2019. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 239 - 240. DOI : 10.1109/A-SSCC47793.2019.9056940.Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space
2019. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019. DOI : 10.1109/ISCAS.2019.8702393.Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems
2019. 30th IEEE Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Istanbul, TURKEY, Sep 08-11, 2019. p. 1021 - 1027. DOI : 10.1109/PIMRC.2019.8904332.Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC
2019. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 285 - 288. DOI : 10.1109/PRIME.2019.8787736.A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications
2019. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 219 - 222. DOI : 10.1109/A-SSCC47793.2019.9056985.FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
2019. 56th ACM/EDAC/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun 02-06, 2019. DOI : 10.1145/3316781.3317830.Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
Ieee Transactions On Circuits And Systems I-Regular Papers. 2018. DOI : 10.1109/TCSI.2018.2803735.On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes
2018. 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing (ISTC), HONG KONG, PEOPLES R CHINA, Dec 03-07, 2018. DOI : 10.1109/ISTC.2018.8625366.Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things
Proceedings Of The IEEE. 2018. DOI : 10.1109/Jproc.2017.2780172.A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI
2018. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018. DOI : 10.1109/ISCAS.2018.8351043.Design and Implementation of a Neural Network Aided Self Interference Cancellation Scheme for Full-Duplex Radios
2018. 52nd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Oct 28-Nov 01, 2018. p. 589 - 593. DOI : 10.1109/ACSSC.2018.8645295.Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster
Ieee Micro. 2017. DOI : 10.1109/MM.2017.3711645.An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2017. DOI : 10.1007/s11265-015-1086-1.Polar codes and APSK modulation - Just good friends
Information Theory and Applications Workshop (ITA), San Diego, CA, USA, Feb. 12-17, 2017.PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2017. DOI : 10.1109/JETCAS.2017.2745704.Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes
ACM Transactions on Design Automation of Electronic Systems. 2017. DOI : 10.1145/3054744.High-Speed Wireline Link Design
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7758.Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders
2017. IEEE Wireless Communications and Networking Conference (WCNC), San Francisco, CA, USA, Mar. 2017. p. 1 - 6. DOI : 10.1109/WCNCW.2017.7919106.Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. DOI : 10.1109/TCSI.2017.2698138.Blind detection of polar codes
2017. IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, October 3-5, 2017. DOI : 10.1109/SiPS.2017.8109977.Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
Acm Transactions On Design Automation Of Electronic Systems. 2016. DOI : 10.1145/2890498.Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016. p. 13:1 - 13:6. DOI : 10.1145/2897937.2898095.Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments
Ieee Transactions On Antennas And Propagation. 2016. DOI : 10.1109/Tap.2016.2624138.Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS
Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2016.2537931.Approximate Computing for Unreliable Silicon
2016. 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). DOI : 10.1109/DTIS.2016.7483878.Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7297.A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS
2016. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016. p. 309 - 312. DOI : 10.1109/ESSCIRC.2016.7598304.Hardware Decoders for Polar Codes: An Overview
2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 149 - 152. DOI : 10.1109/ISCAS.2016.7527192.Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016. DOI : 10.1145/2897937.2696095.A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination
2016. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016. p. 2667 - 2670. DOI : 10.1109/ISCAS.2016.7539142.Modulation, Coding, and Receiver Design for Gigabit mmWave Communication
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7111.Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices
2016. Design, Automation and Test in Europe Conference (DATE '16), Dresden, Germany, March 14-18, 2016. p. 838 - 841.A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code
2016. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2016. p. 1194 - 1198. DOI : 10.1109/ACSSC.2016.7869561.Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2016. DOI : 10.1007/s11265-015-1003-7.Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers
2016. 17th IEEE International workshop on Signal Processing Advances in Wireless Communications, Edinburgh, Scotland, UK, July 3-6, 2016. DOI : 10.1109/SPAWC.2016.7536811.DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment
2016. 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016. p. 261 - 264. DOI : 10.1109/ESSCIRC.2016.7598292.Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency
2016. IEEE 83rd Vehicular Technology Conference, Nanjing, China, 15-18 May. DOI : 10.1109/VTCSpring.2016.7504477.High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding
2016. IEEE Conference on Standards for Communications and Networking (CSCN), Berlin, GERMANY, OCT 31-NOV 02, 2016. DOI : 10.1109/CSCN.2016.7785181.Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs
Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2015.2512706.Microarchitectural Low-Power Design Techniques for Embedded Microprocessors
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7168.Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. DOI : 10.1109/TVLSI.2015.2394459.193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016. 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), Yokohama, Japan, April 20-22, 2016. DOI : 10.1109/CoolChips.2016.7503670.A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design
2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 1006 - 1009. DOI : 10.1109/ISCAS.2016.7527413.Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems
2015. 2015 22nd IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, December 06-09, 2015. p. 637 - 640. DOI : 10.1109/ICECS.2015.7440397.Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications
2015. Design Automation Conference (DAC'15), San Francisco, California, USA, June 7-11, 2015. p. 1 - 6. DOI : 10.1145/2744769.2744871.Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation
2015. 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, Hangzhou, China, 22-25 06 2015. p. 407 - 408. DOI : 10.1145/2746285.2764932.Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression
EURASIP Journal on Wireless Communications and Networking. 2015. DOI : 10.1186/s13638-015-0350-1.Automated Performance Characterization of Dynamic Clock Adjustment Techniques on an OpenRISC ISS
2015An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop
2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7169017.Approximate Computing With Unreliable Dynamic Memories
2015. International New Circuits And Systems Conference (NEWCAS), Grenoble, France, June 7-10, 2015. DOI : 10.1109/NEWCAS.2015.7182027.An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity
Ieee Journal Of Solid-State Circuits. 2015. DOI : 10.1109/Jssc.2015.2417802.Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication
2015. 49th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 8-11, 2015. p. 1133 - 1137. DOI : 10.1109/ACSSC.2015.7421317.An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes
2015. 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015. p. 633 - 636. DOI : 10.1109/ICECS.2015.7440396.Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment
2015. The Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2015. p. 381 - 386. DOI : 10.7873/DATE.2015.0303.Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors
Nanotera Annual Meeting 2015, Bern, Switzerland, May 5, 2015.Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder
2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7168911.Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication
2015. Midwest Symposium on Circuits and Systems, Fort Collins, Colorado, USA, August 2-5, 2015. DOI : 10.1109/MWSCAS.2015.7282089.Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
Acm Transactions On Embedded Computing Systems. 2015. DOI : 10.1145/2656207.LLR-Based Successive Cancellation List Decoding of Polar Codes
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2439211.Power analysis and optimization of on-board processing for the EFM32 microprocessor
2015A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm
2015. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, November 9-11, 2015. p. 193 - 196. DOI : 10.1109/ASSCC.2015.7387455.Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories
2015. DATE 2015, Grenoble, France, March 9-13, 2015. p. 489 - 494. DOI : 10.7873/DATE.2015.0783.Method and apparatus for low complexity spectral analysis of bio-signals
US9760536 ; US2015220486 ; EP2884884 ; WO2014027329 . 2015.Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM
Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2305016.Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing
WO2013136259 ; WO2013136259 . 2014.Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams
University Booth at DATE 2014, Dresden, Germany, March 24-28, 2014.Energy Efficiency through Significance-Based Computing
Computer. 2014. DOI : 10.1109/MC.2014.182.Novel Approaches Toward Area- and Energy-Efficient Embedded Memories
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6074.Hardware Architecture for List Successive Cancellation Decoding of Polar Codes
Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2327336.True MIMO transmission using a single RF-chain and antenna: recent developments
2014. Eucap 2014, 8th European Conf. on Antennas and Prop., The Hague, Netherlands, 2014.A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s
IEEE Transactions on Circuits and Systems I. 2014. DOI : 10.1109/TCSI.2013.2295027.LLR-based Successive Cancellation List Decoding of Polar Codes
2014. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2014), Florence, Italy, May 4-9, 2014. p. 3903 - 3907. DOI : 10.1109/ICASSP.2014.6854333.Low Power Wake-up Receiver
2014Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). p. 3928 - 3932. DOI : 10.1109/ICASSP.2014.6854338.Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform
2014Variability-Aware Design Space Exploration of Embedded Memories
2014. 28th IEEE Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December 3-5, 2014. DOI : 10.1109/EEEI.2014.7005798.A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead
2014. The 12th IEEE International Conference on Embedded and Ubiquitous Computing, Milan, 25-29.08.2014. p. 265 - 272. DOI : 10.1109/EUC.2014.46.Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design
IEEE Transactions on Circuits and Systems Part 1 Regular Papers. 2014. DOI : 10.1109/TCSI.2014.2334891.Correlation Based Phase Noise Compensation in 60 GHz Wireless Systems
2014. 2014 IEEE 28-th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December, 3-5, 2014. DOI : 10.1109/EEEI.2014.7005755.Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage
IEEE Communications Letters. 2014. DOI : 10.1109/Lcomm.2014.030714.132830.4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes
2014. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1-5 June 2014. p. 2177 - 2180. DOI : 10.1109/ISCAS.2014.6865600.Data Compression via Logic Synthesis
2014. 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, January 20-23, 2014. p. 628 - 633. DOI : 10.1109/ASPDAC.2014.6742961.A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability
2014. Design Automation & Test in Europe (DATE), Dresden, Germany. DOI : 10.7873/DATE.2014.184.Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes
2014. IEEE International Symposium on Information Theory, Honolulu, Hawaii, USA, June 29 - July 4, 2014. p. 2977 - 2981. DOI : 10.1109/ISIT.2014.6875380.Cross-Layer Inexact Design for Low-Power Applications
NanoTera Annual Meeting, Lausanne, Switzerland.A Fast and Versatile Quantum Key Distribution System with Hardware Key Distillation and Wavelength Multiplexing
New Journal of Physics. 2014. DOI : 10.1088/1367-2630/16/1/013047.Energy Efficient VLSI Circuits for MIMO-WLAN
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6386.Robust Asynchronous Indoor Localization Using Led Lighting
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014. p. 1866 - 1870. DOI : 10.1109/ICASSP.2014.6853922.Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
Journal of Low Power Electronics and Applications. 2013. DOI : 10.3390/jlpea3020054.Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems
Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013.A Multipurpose Testbed for Full-Duplex Wireless Communications
International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11 2013.Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications
2013. 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vancouver, Canada, May 26-31, 2013. p. 2528 - 2532. DOI : 10.1109/ICASSP.2013.6638111.Impact of body biasing on the retention time of gain-cell memories
The Journal of Engineering. 2013. DOI : 10.1049/joe.2013.0057.An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; Springer, 2013. p. 88 - 106.FireBird: PowerPC e200 Based SoC for High Temperature Operation
2013. IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, USA, September 23-25, 2013. DOI : 10.1109/CICC.2013.6658519.On Self-interference Suppression Methods for Low-complexity Full-duplex MIMO
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 3-6, 2013. p. 992 - 997. DOI : 10.1109/ACSSC.2013.6810439.Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms
2013. The Design, Automation and Test in Europe (DATE), 2013, Grenoble, France. p. 396 - 399. DOI : 10.7873/DATE.2013.090.Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory
2013. Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, March 18-22, 2013. p. 503 - 508. DOI : 10.7873/DATE.2013.114.Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems
2013. 2013 IEEE International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11, 2013. p. 787 - 790. DOI : 10.1109/ICECS.2013.6815532.A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad
2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013. DOI : 10.1109/NEWCAS.2013.6573590.Application-Specific Processor Design for Low-Complexity & Low-Power Embedded Systems
Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013.A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write
2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013. DOI : 10.1109/NEWCAS.2013.6573586.Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis
Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5701.Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies
2012. 7th International Conference on Body Area Networks (BodyNets ’12), Oslo, Norway, September 24-26 2012. p. 52 - 58. DOI : 10.4108/icst.bodynets.2012.249935.On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon
2012. IEEE Design Automation Conference (DAC), San Francisco, June 3-7, 2012. p. 510 - 515. DOI : 10.1145/2228360.2228451.Data Mapping for Unreliable Memories
2012. 50th Annual Allerton Conference on Communication, Control, and Computing, October, 1-5, 2012. p. 679 - 685. DOI : 10.1109/Allerton.2012.6483283.Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time
2012. IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012. p. 2469 - 2472. DOI : 10.1109/ISCAS.2012.6271800.1 Mbps coherent one-way QKD with dense wavelength division multiplexing and hardware key distillation
2nd Annual Conference on Quantum Cryptography (QCRYPT 2012), Singapore, September 10th-14th, 2012.Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture
2012VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2012. DOI : 10.1109/JETCAS.2012.2214636.Layered Detection and Decoding in MIMO Wireless Systems
2012. Conference on Design and Architectures for Signal and Image Processing (DASIP) 2012, Karlsruhe, Germany, October 23-25, 2012.Low-complexity Frequency Synchronization for GSM Systems: Algorithms and Implementation
2012. International Conference on Ultra Modern Telecommunications (ICUMT), St. Petersburg, Russia, October 3-5, 2012.A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
2012. IEEE European Solid-State Circuits Conference (ESSCIRC), Bordeaux, September 17-21, 2012. p. 321 - 324. DOI : 10.1109/ESSCIRC.2012.6341319.A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver
2012. 38th European Solid-State Circuits Conference, Bordeaux, France, September 17-21, 2012.Building a visible light communication system
2012Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM
2012. IEEE International NEWCAS Conference, Montréal, Canada, June 17-20, 2012. p. 77 - 80. DOI : 10.1109/NEWCAS.2012.6328960.Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications
IEEE Transactions on Circuits and Systems for Video Technology. 2012. DOI : 10.1109/Tcsvt.2012.2201671.Low Complexity Spectral Analysis of Heart-Rate-Variability through a Wavelet Based FFT
2012. IEEE Computing in Cardiology (CinC), September, 2012. p. 285 - 288.Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems
2012. IEEE/ACM 2012 Design Automation and Test in Europe conference (DATE), Dresden, Germany, March 12-16, 2012. p. 988 - 994. DOI : 10.1109/DATE.2012.6176640.Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture
2012. IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, CA, USA, October 7-10, 2012. p. 279 - 282. DOI : 10.1109/VLSI-SoC.2012.7332117.Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case
2012. IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012. p. 224 - 231. DOI : 10.1109/FCCM.2012.46.TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
2012. IFIP/IEEE 20th International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, USA, October 7-10, 2012. p. 159 - 164. DOI : 10.1109/VLSI-SoC.2012.7332094.Low-power processor architecture exploration for online biomedical signal analysis
Circuits, Devices & Systems, IET. 2012. DOI : 10.1049/iet-cds.2012.0011.A Sub-VT 2T Gain-Cell Memory for Biomedical Applications
2012. IEEE Subthreshold Microelectronics Conference, Boston, Massachusetts, USA, October 9-10, 2012. DOI : 10.1109/SubVT.2012.6404318.Review and Classification of Gain Cell eDRAM Implementations
2012. DOI : 10.1109/EEEI.2012.6377022.VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems
VLSI-SoC: Forward-Looking Trends in IC and Systems Design; Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. p. 128 - 154.Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems
IEEE International Solid-State Circuits Conference (ISSCC), Student Research Preview (SRP) session, San Francisco, California, USA, February 17-21, 2012.Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture
2012. 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Delft, The Netherlands, July 9-11, 2012. p. 117 - 124. DOI : 10.1109/ASAP.2012.13.System-level implications of residual transmit-RF impairments in MIMO systems
2011. European Conference on Antennas and Propagation, Rome, Italy, April 11-15, 2011. p. 2686 - 2689.Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders
2011. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011. p. 1772 - 1775. DOI : 10.1109/ISCAS.2011.5937927.Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems
2011. IEEE 21st Edition of the Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, May 2-4, 2011. p. 343 - 346. DOI : 10.1145/1973009.1973078.Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing
2011. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS ‘11), Madrid, Spain, September 26-29, 2011. p. 102 - 111. DOI : 10.1007/978-3-642-24154-3_11.Synthesis strategies for sub-VT systems
2011. IEEE European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden, August 29-31, 2011. p. 552 - 555. DOI : 10.1109/ECCTD.2011.6043593.An FPGA-based processing pipeline for high definition stereo video
EURASIP Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-18.A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS Soft-Input Soft-Output Sphere Decoder
2011. IEEE Asian Solid-State Circuits Conference, Jeju, Korea, November 14-16, 2011. p. 297 - 300. DOI : 10.1109/ASSCC.2011.6123571.Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2011. DOI : 10.1109/JETCAS.2011.2162159.Random Sampling ADC for Sparse Spectrum Sensing
2011. European Signal Processing Conference, Barcelona, Spain, August 29 - September 2, 2011.Computational stereo camera system with programmable control loop
2011. ACM SIGGRAPH, Vancouver, Canada, August 7-11, 2011. DOI : 10.1145/2010324.1964989.Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection
2010. 2010 International Conference on Microelectronics (ICM), Cairo, Egypt, 19-22 December 2010. p. 391 - 394. DOI : 10.1109/ICM.2010.5696169.VLSI Implementation of a Low-Complexity LLL Lattice Reduction Algorithm for MIMO Detection
2010. International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), Paris, FRANCE, May 30-Jun 02, 2010. p. 3745 - 3748. DOI : 10.1109/ISCAS.2010.5537742.Matching pursuit: Evaluation and implementatio for LTE channel estimation
2010. 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010, Paris, France, 30 05 - 2 06 2010. p. 589 - 592. DOI : 10.1109/ISCAS.2010.5537528.A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
2010. 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, November 8-10, 2010. p. 1 - 4. DOI : 10.1109/ASSCC.2010.5716618.Towards generic low-power area-efficient standard cell based memory architectures
2010. 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, WA, USA, August 1-4, 2010. p. 129 - 132. DOI : 10.1109/MWSCAS.2010.5548579.MIMO transmission with residual transmit-RF impairments
2010. 2010 International ITG Workshop on Smart Antennas (WSA), Bremen, Germany, 23-24 02 2010. p. 189 - 196. DOI : 10.1109/WSA.2010.5456453.Low-complexity Seysen's algorithm based lattice reduction-aided MIMO detection for hardware implementations
2010. 2010 44th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 7-10 November 2010. p. 1468 - 1472. DOI : 10.1109/ACSSC.2010.5757780.Area- and throughput-optimized VLSI architecture of sphere decoding
2010. 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, 27-29 09 2010. p. 189 - 194. DOI : 10.1109/VLSISOC.2010.5642593.Simulation and Emulation of MIMO Wireless Baseband Transceivers
Eurasip Journal On Wireless Communications And Networking. 2010. DOI : 10.1155/2010/196796.The effect of unreliable LLR storage on the performance of MIMO-BICM
2010. 2010 44th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 7-10 November 2010. p. 736 - 740. DOI : 10.1109/ACSSC.2010.5757661.A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS
2009. Symposium on VLSI Circuits, Kyoto, JAPAN, Jun 16-18, 2009. p. 282 - 283.Design and Optimization of an HSDPA Turbo Decoder ASIC
IEEE Journal of Solid-State Circuits. 2009. DOI : 10.1109/JSSC.2008.2007166.Implementation of a 2x2 MIMO-OFDM receiver on an application specific processor
2009. International Conference on Microelectronics, Cairo, EGYPT, Dec 29-31, 2007. p. 1642 - 1649. DOI : 10.1016/j.mejo.2009.02.005.A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS
2008. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 03-07, 2008. p. 264 - 265+612. DOI : 10.1109/ISSCC.2008.4523158.Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes
2008. 42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 26-29, 2008. p. 1137 - 1142. DOI : 10.1109/ACSSC.2008.5074592.Soft-output sphere decoding: Algorithms and VLSI implementation
2008. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 02, 2006. p. 290 - 300. DOI : 10.1109/JSAC.2008.080206.A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization
Ieee Journal On Selected Areas In Communications. 2008. DOI : 10.1109/JSAC.2008.080805.Regularized frequency domain equalization algorithm and its VLSI implementation
2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 3530 - 3533. DOI : 10.1109/ISCAS.2007.378444.An IEEE 802.11a baseband receiver implementation on an application specific processor
2007. 50th Midwest Symposium on Circuits and Systems, Montreal, CANADA, Sep 05, 2007-Aug 08, 2008. p. 1066 - 1069.VLSI implementation of a high-speed iterative sorted MMSE QR decomposition
2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 1421 - 1424. DOI : 10.1109/ISCAS.2007.378495.VLSI implementation of a lattice-reduction algorithm for multi-antenna broadcast precoding
2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 673 - 676. DOI : 10.1109/ISCAS.2007.377898.FFT processor for OFDM channel estimation
2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 1417 - 1420. DOI : 10.1109/ISCAS.2007.378494.Soft-output sphere decoding: Performanceand implementation aspects
2006. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 01, 2006. p. 2071 - 2076. DOI : 10.1109/ACSSC.2006.355132.A unification of ML-optimal tree-search decoders
2006. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 01, 2006. p. 2185 - 2189. DOI : 10.1109/ACSSC.2006.355156.Silicon implementation of an MMSE-based soft demapper for MIMO-BICM
2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 2597 - 2600. DOI : 10.1109/ISCAS.2006.1693155.VLSI implementation of the list sphere algorithm
2006. 24th Norchip Conference, Linkoping, SWEDEN, Nov 20-21, 2006. p. 107 - 110. DOI : 10.1109/NORCHP.2006.329255.K-Best MIMO detection VLSI architectures achieving up to 424 mbps
2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 1151 - 1154. DOI : 10.1109/ISCAS.2006.1692794.Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems
2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 4102 - 4105. DOI : 10.1109/ISCAS.2006.1693531.Advanced receiver algorithms for MIMO wireless communications
2006. Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Munich, GERMANY, Mar 06-10, 2006. p. 591 - 596. DOI : 10.1109/DATE.2006.243974.A frame-start detector for a 4x4 MIMO-OFDM system
2006. 31st IEEE International Conference on Acoustics, Speech and Signal Processing, Toulouse, FRANCE, May 14-19, 2006. p. 4095 - 4098. DOI : 10.1109/ICASSP.2006.1660996.FPGA implementation of Viterbi decoders for MIMO-BICM
2005. 39th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 30-Nov 02, 2005. p. 734 - 738. DOI : 10.1109/ACSSC.2005.1599849.ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs
2005. 31st European Solid-State Circuits Conference, Grenoble, FRANCE, Sep 12-16, 2005. p. 215 - 218. DOI : 10.1109/ESSCIR.2005.1541598.Receiver design for multi-antenna wireless communications
2005. International Conference on PhD Research in Microelectronics and Electronics (PRIME 2005), Lausanne, SWITZERLAND, 2005. p. 231 - 234. DOI : 10.1109/RME.2005.1542930.VLSI implementation of MIMO detection using the sphere decoding algorithm
2005. 30th European Solid-State Circuits Conference (ESSCIRC 2004), Leuven, BELGIUM, Sep 21-23, 2004. p. 1566 - 1577. DOI : 10.1109/JSSC.2005.847505.Interpolation-based QR decomposition in MIMO-OFDM systems
2005. 6th IEEE Workshop on Signal Processing Advances in Wireless Communications, New York, NY, Jun 05-08, 2005. p. 945 - 949. DOI : 10.1109/SPAWC.2005.1506279.Low complexity frequency domain equalization of MIMO channels with applications to MIMO-CDMA systems
2004. 58th IEEE Vehicular Technology Conference (VTC 2003), Orlando, FL, Oct 06-09, 2003. p. 468 - 472. DOI : 10.1109/VETECF.2003.1285061.Performance of MIMO-extended UMTS-FDD downlink comparing space-time RAKE and linear equalizer
2004. 58th IEEE Vehicular Technology Conference (VTC 2003), Orlando, FL, Oct 06-09, 2003. p. 473 - 477. DOI : 10.1109/VETECF.2003.1285062.VLSI implementation of the sphere decoding algorithm
2004. 30th European Solid-State Circuits Conference (ESSCIRC 2004), Leuven, BELGIUM, Sep 21-23, 2004. p. 303 - 306. DOI : 10.1109/ESSCIR.2004.1356678.Efficient ASIC implementation of a real-time depth mapping stereo vision system
2003. 46th IEEE International Midwest Symposium on Circuits and Systems, Cairo, EGYPT, Dec 27-30, 2003. p. 1478 - 1481. DOI : 10.1109/MWSCAS.2003.1562575.Rapid prototyping for wireless designs: the five-ones approach
Signal Processing. 2003. DOI : 10.1016/S0165-1684(03)00090-2.A 50 MBPS 4x4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation
2003. 10th IEEE International Conference on Electronics, Circuits and Systems, Sharjah, U ARAB EMIRATES, Dec 14-17, 2003. p. 332 - 335. DOI : 10.1109/ICECS.2003.1302044.Programmable code processor for software defined radio
2003. 37th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov 09-12, 2003. p. 2156 - 2160. DOI : 10.1109/ACSSC.2003.1292362.Variable delay ripple carry adder with carry chain interrupt detection
2003. IEEE International Symposium on Circuits and Systems, BANGKOK, THAILAND, May 25-28, 2003. p. 113 - 116. DOI : 10.1109/ISCAS.2003.1206202.Practical low complexity linear equalization for MIMO-CDMA systems
2003. 37th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov 09-12, 2003. p. 1266 - 1272. DOI : 10.1109/ACSSC.2003.1292192.An ASIC implementation of adaptive arithmetic coding
2002. 36th Asilomar Conference on Signals, Systems and Computers, PACIFIC GROVE, CA, Nov 03-06, 2002. p. 1078 - 1083. DOI : 10.1109/ACSSC.2002.1196950.Rapid prototyping design of a 4x4 BLAST-over-UMTS system
2001. 35th Asilomar Conference on Signals, Systems and Computers, PACIFIC GROVE, CA, Nov 04-07, 2001. p. 1256 - 1260. DOI : 10.1109/ACSSC.2001.987692.A 3D-DCT real-time video compression system for low complexity single-chip VLSI implementation
2000. Mobile Multimedia Conference, MoMuC 2000, Tokyo, Japan, November, 2000.From basic concept to real-time implementation: Prototyping WCDMA downlink receiver algorithms - A case study
2000. 34th Asilomar Conference on Signals, Systems, and Computers, PACIFIC GROVE, CA, Oct 29-Nov 01, 2000. p. 84 - 88. DOI : 10.1109/ACSSC.2000.910922.Teaching & PhD
Courses
Digital systems design
Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware.
They learn how to design synchronous digital circuits on register transfer level, analyse their timing and implement them in VHDL and on FPGAs.
Systèmes de télécommunications
Learning basic knowledge on transmission of information and identify the relevant criteria for the dimensioning of a telecommunication system. Evaluate the quality of digital transmission systems (error probability) either in baseband or shifted passband.
Lab in information technologies
Get familiar with experimental aspects of the main domains of the orientation "Information and communication technologies"
Fundamentals of VLSI design
The course introduces the fundamentals of digital integrated circuits and the technology aspects from a designers perspective. It focuses mostly on transistor level, but discusses also the extension to large digital semicustom designs.
Wireless receivers: algorithms and architectures
The students will learn about the basic principles of wireless communication systems, including transmission and modulation schemes as well as the basic components and algorithms of a wireless receiver. They develop an understanding for the wireless channel and system performance and limitations.
Lab in advanced VLSI design
this class covers advanced VLSI design techniques. top-down full custom circuit design.
Design and Optimization of Internet-of-Things Systems
This course provides a complete overview of the most relevant subfields related to Internet of Things (IoT) systems, it presents the perspectives and the underlying technologies, with a particular focus on edge AI architectures and software (AI and TinyML algorithms), communication and Cloud systems
Energy Autonomous Wireless Smart Systems
The course provides in depth knowledge on how to design an energy autonomous microsystem embedding sensors with wireless transmission of information. It covers the energy generation, power management, and data processing and transmission with an emphasis on low-power and energy efficient operation.