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BiographyMirjana Stojilović received the Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. From 2010 to 2013, she was collaborating with the Processor Architecture Laboratory at EPFL, visiting periodically as a Guest Researcher. From 2013 to 2016, she worked at the University of Applied Sciences Western Switzerland as a senior researcher, and at EPFL as a lecturer. She joined Parallel Systems Architecture Lab at EPFL in October 2016.
Mirjana's main research interests span the areas of field-programmable technology, electronic design automation (EDA), and, more recently, electrical-level attacks and countermeasures for reconfigurable hardware.
Mirjana Stojilović serves on the program committee of the FPGA, FCCM, FPL, and DATE conferences and as a reviewer for IEEE TCAD, TVLSI, TC, TEMC, IEEE Access, IEEE TPDS, and ACM TRETS. She is an associate editor for IEEE ESL and ACM TRETS. In 2021, she was on the Best Paper Award (BPA) committee of the FPGA conference. In 2020, she was nominated for the BPA at the International Conference on Field-Programmable Technology (FPT). Mirjana received the Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016), Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016), and the Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012). In 2015, the EPFL School of Computer and Communication Sciences (IC) presented her with the Teaching Award.
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs2023-04-19. Design, Automation and Test in Europe Conference DATE 2023, Antwerp, Belgium, April 17-19, 2023.
The Side-channel Metrics Cheat SheetACM Computing Surveys. 2023-02-02. DOI : 10.1145/3565571.
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting AttacksIEEE Access. 2022-12-22. DOI : 10.1109/ACCESS.2022.3231753.
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time2022-03-22. 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), Antwerp, Belgium [Virtual], March 14-23, 2022. p. 670-675. DOI : 10.23919/DATE54114.2022.9774531.
FPGA-to-CPU Undervolting Attacks2022-03-22. 25th Design, Automation and Test in Europe, Antwerp, Belgium [Virtual], March 14-23, 2022. p. 999-1004. DOI : 10.23919/DATE54114.2022.9774663.
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous EraACM Computing Surveys. 2022-02-03. DOI : 10.1145/3498337.
Deep Learning Detection of GPS Spoofing2022-02-02. 7th International Conference Machine Learning, Optimization, and Data Science (LOD 2021), Grasmere, UK, October 4-8, 2021. p. 527-540. DOI : 10.1007/978-3-030-95467-3_38.
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs2021-03-01. International Symposium on Field-Programmable Gate Arrays, Virtual Conference, February 28 - March 2, 2021. DOI : 10.1145/3431920.3439285.
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks2021-02-04. DATE 2021 Design, Automation and Test in Europe, Virtual, February 1-5, 2021. p. 1645-1650. DOI : 10.23919/DATE51398.2021.9473947.
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced RoutingIEEE Access. 2021. DOI : 10.1109/ACCESS.2021.3085005.
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs2020-12-01. 19th International Conference on Field-Programmable Technology (ICFPT), Maui, HI, USA (Virtual conference), December 7-11, 2020. p. 288-289. DOI : 10.1109/ICFPT51103.2020.00050.
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?2020-03-09. Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2020. p. 1007-1010. DOI : 10.23919/DATE48585.2020.9116481.
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs2020-02-23. 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, California, USA, February 23-25, 2020. DOI : 10.1145/3373087.3375318.
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks2020-02-23. 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, California, USA, February 23-25, 2020. DOI : 10.1145/3373087.3375319.
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer2020-01-08. 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems (VLSID), Bangalore, India, January 4-8, 2020. DOI : 10.1109/VLSID49098.2020.00031.
X-Attack: Remote Activation of Satisfiability Don’t-Care Hardware Trojans on Shared FPGAs2020. 30th International Conference on Field-Programmable Logic and Applications (FPL), ELECTR NETWORK, August 31 - September 4, 2020. p. 185-192. DOI : 10.1109/FPL50879.2020.00039.
A machine learning approach for power gating the FPGA routing network2019-12-11. 2019 International Conference on Field-Programmable Technology (ICFPT), Tianjin, China, December 9-13, 2019. p. 10-18. DOI : 10.1109/ICFPT47387.2019.00010.
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey2019-09-08. 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September 9 - 13, 2019. DOI : 10.1109/FPL.2019.00039.
FPGA-Assisted Deterministic Routing for FPGAs2019-05-20. 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Rio de Janeiro, Brasil, May 20-24, 2019. p. 155-162. DOI : 10.1109/IPDPSW.2019.00034.
Timing Violation Induced Faults in Multi-Tenant FPGAs2019-03-25. Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ITALY, Mar 25-29, 2019. p. 1745-1750. DOI : 10.23919/DATE.2019.8715263.
Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model2018-01-01. 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, IRELAND, Aug 26-31, 2018. p. 21-25. DOI : 10.1109/FPL.2018.00011.
Development of a Lightning Location System Based on Electromagnetic Time Reversal: Technical Challenges and Expected Gain2018. 2018 International Lightning Detection Conference (ILDC), Fort Lauderdale, FL, USA, March 12-15, 2018.
Parallel FPGA routing: Survey and challenges2017-01-01. 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 4-8, 2017. p. 1-8. DOI : 10.23919/FPL.2017.8056782.
Lightning Location Systems and Interstroke Intervals: Effects of Imperfect Detection Efficiency2016. 33rd International Conference on Lightning Protection (ICLP), Estoril, Portugal, September 25-30, 2016. DOI : 10.1109/ICLP.2016.7791370.
Protection Strategy against IEMI for Wireless Communication Infrastructures2016. 2016 International Symposium on Electromagnetic Compatibility - EMC Europe, Wroclaw, Poland, September 5-10, 2016. p. 455-460. DOI : 10.1109/EMCEurope.2016.7739189.
Evaluation of The Electric-Field Transfer Functions Between IEMI Sources and Banking IT Equipment2015. Joint IEEE International Symposium on EMC and EMC Europe, Dresden, Germany, August 16-22, 2015. p. 1345-1350. DOI : 10.1109/ISEMC.2015.7256367.
The European Project STRUCTURES: Challenges and Results2015. Joint IEEE International Symposium on EMC and EMC Europe, Dresden, Germany, August 16-22, 2015. p. 1095-1100. DOI : 10.1109/ISEMC.2015.7256321.
A Comparator-based Technique for Identification of Intentional Electromagnetic Interference Attacks2014. International Symposiumm on Electromagnetic Compatibility - EMC Europe 2014, Gothenburg, Sweden, September 1-4, 2014.
Influence of LLS Detection Efficiency on the Measured Distribution of Interstroke Intervals2014. American Electromagnetics International Symposium (AMEREM), Albuquerque, New Mexico, USA, July 27-31, 2014.
Selective Flexibility: Creating Domain-Specific Reconfigurable ArraysIeee Transactions On Computer-Aided Design Of Integrated Circuits And Systems. 2013. DOI : 10.1109/Tcad.2012.2235127.
dblp - Mirjana Stojilovic
Google Scholar - Mirjana Stojilovic
Teaching & PhD
PhD StudentsCoulon Louis, Glamocanin Ognjen, Mahmoud Dina Gamaleldin Ahmed Shawky, Shrivastava Shashwat,
Semester and Diploma ProjectsIf you are passionate about hardware security, FPGAs, design automation, machine learning, side-channel attacks, cloud computing, parallel CPU/FPGA/GPU computing, or embedded system design, contact me.
Our current project ideas can be found on this link. Additionally, we offer one project in collaboration with Cyber Defence Campus, armasuisse; more details can be found here: link.
These are only some topics we'd be happy to work on. If interested to hear more, don't hesitate to contact me; I'd be glad to try to find other topics that would be of mutual interest.
Semester projects and MSc Theses completed in my research group:
-- MSc Thesis, David Spielmann: Routing delay sensors for remote power side-channel attacks on FPGAs
-- Lucien Bart: Evaluating and enhancing the performance of MetriSCA Library
-- Pierre Colson: Remote attacks on FPGA clock networks
-- David Dervishi: FPGA-to-CPU fault-injection attacks
-- David Spielmann: Power side-channel analysis on remotely accessible FPGAs
-- Anton Hosgood: Titan benchmark suite: From VTR to Xilinx FPGAs
-- Léa Michelaud: Threshold Implementation of a Block Cipher
-- Arthur Passuello: Remote power side-channel disassembly attacks on ARM-based FPGA SoCs
-- Cédric Holzl: FPGA routing with limited crosstalk side-channel attack opportunities
-- MSc Thesis, Hédi Fendri: ML-based side-channel analysis and disassembly of hardware Root of Trust (Recipient of the Omega Student Award)
-- Cédric Holzl: Secure routing against crosstalk-attacks on FPGAs
-- Morten Petersen: Xilinx Series-7 FPGA Routing Architecture Analysis
-- Gaietan Renault: Experimental comparison of voltage sensors on FPGAs
-- Markus Ding: Parallel FPGA Router compatible with VPR 8.0
-- Dorian Ros: Mutual Information analysis of an FPGA implementation of the AES encryption algorithm
-- Mathieu Caboche: GPU acceleration of electromagnetic time-reversal algorithm
-- Sacha Coppey: Design and performance evaluation of dataflow-enabled domain-specific CGRAs
-- Ahmed Ben Haj Yahia: Customizing FPGA Designs using RapidWright
-- Alexandre Abbey: Differential power analysis attack on an FPGA implementation of AES algorithm
-- Robin Mamie: Designing a multicycle processor in Chisel
-- Frédéric Gessler: A shared-memory parallel implementation of the RePlAce global cell placement algorithm
-- Markus Ding: FPGA Trojan for controlled voltage drop injection
-- Ugo Damiano: Step response characterization of FPGA power delivery networks
-- MSc Thesis, Dario Korolija: FPGA-based hardware acceleration of FPGA routing
-- Alex Ferragni: Attack on Altera FPGAs using bitstreams
-- Martin Chatton: Parallel FPGA routing using recursive net-partitioning