Mirjana Stojilovic

INJ 235 (Bâtiment INJ)
Station 14
CH-1015 Lausanne

Web site:  Web site:  https://parsa.epfl.ch/

INN 112 (Bâtiment INN)
Station 14
CH-1015 Lausanne

Web site:  Web site:  https://sin.epfl.ch

INR 130 (Bâtiment INR)
Station 14
CH-1015 Lausanne

Web site:  Web site:  https://ssc.epfl.ch

Administrative data


Infoscience publications

Other publications

Teaching & PhD


Computer Science

Communication Systems

PhD Programs

Doctoral program in computer and communication sciences

Semester and Diploma Projects

If you are passionate about hardware security, FPGAs, design automation, machine learning, side-channel attacks, cloud computing, parallel CPU/FPGA/GPU computing, or embedded system design, contact me.

Our current project ideas can be found on this link, but these are not the only topics we'd be happy to work on. If interested to hear more, don't hesitate to contact me; I'd be happy to try to find other topics that would be of mutual interest.

Students who completed their semester projects or MSc Theses under my supervision:
-- Anton Hosgood: Titan benchmark suite: From VTR to Xilinx FPGAs
-- Léa Michelaud: Threshold Implementation of a Block Cipher
-- Arthur Passuello: Remote power side-channel disassembly attacks on ARM-based FPGA SoCs
-- Cédric Holzl: FPGA routing with limited crosstalk side-channel attack opportunities

-- MSc Thesis, Hédi Fendri: ML-based side-channel analysis and disassembly of hardware Root of Trust (Recipient of the Omega Student Award)
-- Cédric Holzl: Secure routing against crosstalk-attacks on FPGAs
-- Morten Petersen: Xilinx Series-7 FPGA Routing Architecture Analysis
-- Gaietan Renault: Experimental comparison of voltage sensors on FPGAs
-- Markus Ding: Parallel FPGA Router compatible with VPR 8.0
-- Dorian Ros: Mutual Information analysis of an FPGA implementation of the AES encryption algorithm
-- Mathieu Caboche: GPU acceleration of electromagnetic time-reversal algorithm
-- Sacha Coppey: Design and performance evaluation of dataflow-enabled domain-specific CGRAs
-- Ahmed Ben Haj Yahia: Customizing FPGA Designs using RapidWright

-- Alexandre Abbey: Differential power analysis attack on an FPGA omplementation of AES algorithm
-- Robin Mamie: Designing a multicycle processor in Chisel
-- Frédéric Gessler: A shared-memory parallel implementation of the RePlAce global cell placement algorithm
-- Markus Ding: FPGA Trojan for controlled voltage drop injection
-- Ugo Damiano: Step response characterization of FPGA power delivery networks

-- MSc Thesis, Dario Korolija: FPGA-based hardware acceleration of FPGA routing
-- Alex Ferragni: Attack on Altera FPGAs using bitstreams
-- Martin Chatton: Parallel FPGA routing using recursive net-partitioning


Information, Computation, Communication

(Coursebook not yet approved by the section)

Information, Computation, Communication

(Coursebook not yet approved by the section)