BiographyMirjana Stojilović received the Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. From 2010 to 2013, she was collaborating with the Processor Architecture Laboratory at EPFL, visiting periodically as a Guest Researcher. From 2013 to 2016, she was working at the University of Applied Sciences Western Switzerland as a senior researcher, and at EPFL as a lecturer. She joined Parallel Systems Architecture Lab at EPFL in October 2016.
Mirjana's main research interests include electronic design automation, reconfigurable computing, electromagnetic-compatibility and signal-integrity issues, and hardware security.
Mirjana Stojilović serves on the program committee of the FPGA, FPL, and FCCM conferences and as a reviewer for IEEE TCAD, TVLSI, TC, TEMC, IEEE Access and ACM TRETS. She received the Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016), Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016), and the Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012). In 2015, the EPFL School of Computer and Communication Sciences (IC) presented her with the Teaching Award.
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time2022-03-22. 25th Design, Automation and Test in Europe - DATE 2022, Antwerp, Belgium [Virtual], March 14-23, 2022.
FPGA-to-CPU Undervolting Attacks2022-03-22. 25th Design, Automation and Test in Europe - DATE 2022 , Antwerp, Belgium [Virtual], March 14-23, 2022.
Deep Learning Detection of GPS Spoofing2022-02-02. 7th International Conference Machine Learning, Optimization, and Data Science (LOD 2021), Grasmere, UK, October 4-8, 2021. p. 527-540. DOI : 10.1007/978-3-030-95467-3_38.
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs2020-12-01. 19th International Conference on Field-Programmable Technology (ICFPT), Maui, HI, USA (Virtual conference), December 7-11, 2020. p. 288-289. DOI : 10.1109/ICFPT51103.2020.00050.
FPGA-Assisted Deterministic Routing for FPGAs2019-05-20. 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Rio de Janeiro, Brasil, May 20-24, 2019. p. 155-162. DOI : 10.1109/IPDPSW.2019.00034.
Development of a Lightning Location System Based on Electromagnetic Time Reversal: Technical Challenges and Expected Gain2018. 2018 International Lightning Detection Conference (ILDC), Fort Lauderdale, FL, USA, March 12-15, 2018.
Parallel FPGA routing: Survey and challenges2017-01-01. 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 4-8, 2017. p. 1-8. DOI : 10.23919/FPL.2017.8056782.
Lightning Location Systems and Interstroke Intervals: Effects of Imperfect Detection Efficiency2016. 33rd International Conference on Lightning Protection (ICLP), Estoril, Portugal, September 25-30, 2016. DOI : 10.1109/ICLP.2016.7791370.
Protection Strategy against IEMI for Wireless Communication Infrastructures2016. 2016 International Symposium on Electromagnetic Compatibility - EMC Europe, Wroclaw, Poland, September 5-10, 2016. p. 455-460. DOI : 10.1109/EMCEurope.2016.7739189.
Evaluation of The Electric-Field Transfer Functions Between IEMI Sources and Banking IT Equipment2015. Joint IEEE International Symposium on EMC and EMC Europe, Dresden, Germany, August 16-22, 2015. p. 1345-1350. DOI : 10.1109/ISEMC.2015.7256367.
The European Project STRUCTURES: Challenges and Results2015. Joint IEEE International Symposium on EMC and EMC Europe, Dresden, Germany, August 16-22, 2015. p. 1095-1100. DOI : 10.1109/ISEMC.2015.7256321.
A Comparator-based Technique for Identification of Intentional Electromagnetic Interference Attacks2014. International Symposiumm on Electromagnetic Compatibility - EMC Europe 2014, Gothenburg, Sweden, September 1-4, 2014.
Influence of LLS Detection Efficiency on the Measured Distribution of Interstroke Intervals2014. American Electromagnetics International Symposium (AMEREM), Albuquerque, New Mexico, USA, July 27-31, 2014.
Selective Flexibility: Creating Domain-Specific Reconfigurable ArraysIeee Transactions On Computer-Aided Design Of Integrated Circuits And Systems. 2013. DOI : 10.1109/Tcad.2012.2235127.
dblp: Mirjana Stojilovic
Teaching & PhD
Doctoral program in computer and communication sciences
Semester and Diploma ProjectsIf you are passionate about hardware security, FPGAs, design automation, machine learning, side-channel attacks, cloud computing, parallel CPU/FPGA/GPU computing, or embedded system design, contact me.
Our current project ideas can be found on this link, but these are not the only topics we'd be happy to work on. If interested to hear more, don't hesitate to contact me; I'd be happy to try to find other topics that would be of mutual interest.
Students who completed their semester projects or MSc Theses under my supervision:
-- Anton Hosgood: Titan benchmark suite: From VTR to Xilinx FPGAs
-- Léa Michelaud: Threshold Implementation of a Block Cipher
-- Arthur Passuello: Remote power side-channel disassembly attacks on ARM-based FPGA SoCs
-- Cédric Holzl: FPGA routing with limited crosstalk side-channel attack opportunities
-- MSc Thesis, Hédi Fendri: ML-based side-channel analysis and disassembly of hardware Root of Trust (Recipient of the Omega Student Award)
-- Cédric Holzl: Secure routing against crosstalk-attacks on FPGAs
-- Morten Petersen: Xilinx Series-7 FPGA Routing Architecture Analysis
-- Gaietan Renault: Experimental comparison of voltage sensors on FPGAs
-- Markus Ding: Parallel FPGA Router compatible with VPR 8.0
-- Dorian Ros: Mutual Information analysis of an FPGA implementation of the AES encryption algorithm
-- Mathieu Caboche: GPU acceleration of electromagnetic time-reversal algorithm
-- Sacha Coppey: Design and performance evaluation of dataflow-enabled domain-specific CGRAs
-- Ahmed Ben Haj Yahia: Customizing FPGA Designs using RapidWright
-- Alexandre Abbey: Differential power analysis attack on an FPGA omplementation of AES algorithm
-- Robin Mamie: Designing a multicycle processor in Chisel
-- Frédéric Gessler: A shared-memory parallel implementation of the RePlAce global cell placement algorithm
-- Markus Ding: FPGA Trojan for controlled voltage drop injection
-- Ugo Damiano: Step response characterization of FPGA power delivery networks
-- MSc Thesis, Dario Korolija: FPGA-based hardware acceleration of FPGA routing
-- Alex Ferragni: Attack on Altera FPGAs using bitstreams
-- Martin Chatton: Parallel FPGA routing using recursive net-partitioning