Administrative data

Alexandre Sébastien Julien Levisse

alexandre.levisse@epfl.ch +41 21 693 13 46

EPFL STI PAT-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › STI › PAT › PAT-GE

EPFL STI STI-SEL-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › STI › STI-SEL › SEL-GE

EPFL STI PAT-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › STI › IEM › ESL

Website: https://esl.epfl.ch

EPFL STI PAT-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › STI › STI-SEL › SEL-ENS

EPFL STI PAT-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › STI › IEM › AQUA

Website: https://aqua.epfl.ch/

EPFL STI PAT-GE
ELG 030 (Bâtiment ELG)Station 111015 Lausanne

+41 21 693 13 46
Office: ELG 030
EPFL › P › P-EM › CCE

Website: https://cce.epfl.ch/

Biography Teaching & PhD

Education

3D high density memory based on emering resistive technologies : circuit and architecture design

| Microelectronics

2014 – 2017 CEA-Leti

Teaching & PhD

Courses

Fundamentals of VLSI design

EE-429

The course introduces the fundamentals of digital integrated circuits and the technology aspects from a designers perspective. It focuses mostly on transistor level, but discusses also the extension to large digital semicustom designs.

Lab in advanced VLSI design

EE-490(b)

this class covers advanced VLSI design techniques. top-down full custom circuit design.