Andreas Peter Burg
andreas.burg@epfl.ch +41 21 693 69 24
EPFL STI IEL TCL
ELD 130 (Bâtiment ELD)
Station 11
CH-1015 Lausanne
41 21 693 69 24
41 21 693 10 36
Local: ELD 130
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Biography
Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006.In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory.
In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor.
In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP).
Research interests and expertise
* Circuits and systems for telecommunications (wireless and wired)
* Prototyping and silicon implementation of new communication technologies
* Development of communication algorithms and optimization for hardware implementation
* Low-power VLSI signal processing for communications and other applications
* Digital integrated circuits
* Circuits for image and video processing
Publications
Publications Infoscience
Infoscience
Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding
Ieee Transactions On Vehicular Technology. 2021-02-01. DOI : 10.1109/TVT.2021.3052550.Adaptive Body Biasing in Strong Body Factor Technologies
Lausanne, EPFL, 2021. DOI : 10.5075/epfl-thesis-10483.Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations
Ieee Journal On Emerging And Selected Topics In Circuits And Systems. 2020-06-01. DOI : 10.1109/JETCAS.2020.2999944.Hardware Implementation of Neural Self-Interference Cancellation
Ieee Journal On Emerging And Selected Topics In Circuits And Systems. 2020-06-01. DOI : 10.1109/JETCAS.2020.2992370.Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space
Ieee Transactions On Circuits And Systems I-Regular Papers. 2020-04-01. DOI : 10.1109/TCSI.2020.2971695.Design and Decoding of Irregular LDPC Codes Based on Discrete Message Passing
Ieee Transactions On Communications. 2020-03-01. DOI : 10.1109/TCOMM.2019.2944159.Gain-Cell Embedded DRAMs: Modeling and Design Space
Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2020-03-01. DOI : 10.1109/TVLSI.2019.2955933.On the Error Rate of the LoRa Modulation With Interference
Ieee Transactions On Wireless Communications. 2020-02-01. DOI : 10.1109/TWC.2019.2952584.Identification of Non-Linear RF Systems Using Backpropagation
2020-01-01. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICCWorkshops49005.2020.9145367.Training Channel Selection for Learning-based 1-bit Precoding in Massive MU-MIMO
2020-01-01. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICCWorkshops49005.2020.9145443.An Open-Source LoRa Physical Layer Prototype on GNU Radio
2020-01-01. 21st IEEE International Workshop on Signal Processing Advances in Wireless Communications (IEEE SPAWC), ELECTR NETWORK, May 26-29, 2020. DOI : 10.1109/SPAWC48557.2020.9154273.Coded LoRa Frame Error Rate Analysis
2020-01-01. IEEE International Conference on Communications (IEEE ICC) / Workshop on NOMA for 5G and Beyond, ELECTR NETWORK, Jun 07-11, 2020. DOI : 10.1109/ICC40277.2020.9148806.Lupulus: A Flexible Hardware Accelerator For Neural Networks
2020-01-01. IEEE International Conference on Acoustics, Speech, and Signal Processing, Barcelona, SPAIN, May 04-08, 2020. p. 1608-1612. DOI : 10.1109/ICASSP40776.2020.9054764.Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10353.Physical Layer Aspects of LoRa and Full-Duplex Wireless Transceivers
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10258.A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
Ieee Journal Of Solid-State Circuits. 2020-01-01. DOI : 10.1109/JSSC.2019.2938414.GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI
Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2019-12-01. DOI : 10.1109/TCSII.2019.2896164.2019 International Symposium on Low Power Electronics and Design
Ieee Design & Test. 2019-12-01. DOI : 10.1109/MDAT.2019.2941713.Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems
2019-01-01. 30th IEEE Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Istanbul, TURKEY, Sep 08-11, 2019. p. 1021-1027. DOI : 10.1109/PIMRC.2019.8904332.A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET
2019-01-01. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 239-240. DOI : 10.1109/A-SSCC47793.2019.9056940.A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications
2019-01-01. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 219-222. DOI : 10.1109/A-SSCC47793.2019.9056985.Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios
2019-01-01. 53rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Nov 03-06, 2019. p. 1149-1153. DOI : 10.1109/IEEECONF44664.2019.9048900.LoRa Symbol Error Rate Under Non-Aligned Interference
2019-01-01. 53rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Nov 03-06, 2019. p. 1957-1961. DOI : 10.1109/IEEECONF44664.2019.9048665.A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS
2019-01-01. 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr 14-17, 2019. DOI : 10.1109/CICC.2019.8780199.JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS
2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 101-104. DOI : 10.1109/PRIME.2019.8787786.Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC
2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 285-288. DOI : 10.1109/PRIME.2019.8787736.Lora Digital Receiver Analysis And Implementation
2019-01-01. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1498-1502. DOI : 10.1109/ICASSP.2019.8683504.Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space
2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019. DOI : 10.1109/ISCAS.2019.8702393.3.5 GHz Coverage Assessment with a 5G Testbed
2019-01-01. 89th IEEE Vehicular Technology Conference (VTC Spring), Kuala Lumpur, MALAYSIA, Apr 28-May 01, 2019. DOI : 10.1109/VTCSpring.2019.8746551.FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
2019-01-01. 56th ACM/EDAC/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun 02-06, 2019. DOI : 10.1145/3316781.3317830.A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
2019-01-01. IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, Feb 17-21, 2019. p. 476-478. DOI : 10.1109/ISSCC.2019.8662505.Low-Power Design of Digital VLSI Circuits around the Point of First Failure
Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9180.Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
Ieee Transactions On Circuits And Systems I-Regular Papers. 2018-10-01. DOI : 10.1109/TCSI.2018.2803735.Design and Implementation of a Neural Network Aided Self Interference Cancellation Scheme for Full-Duplex Radios
2018-01-01. 52nd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Oct 28-Nov 01, 2018. p. 589-593. DOI : 10.1109/ACSSC.2018.8645295.On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes
2018-01-01. 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing (ISTC), HONG KONG, PEOPLES R CHINA, Dec 03-07, 2018. DOI : 10.1109/ISTC.2018.8625366.Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel
IEEE TRANSACTIONS ON COMMUNICATIONS. 2018. DOI : 10.1109/TCOMM.2017.2771243.Fast-SSC-Flip Decoding of Polar Codes
2018. DOI : 10.1109/WCNCW.2018.8369026.An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications
IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2018. DOI : 10.1109/JSSC.2018.2820145.A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2018. DOI : 10.1109/TVLSI.2017.2766925.A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. DOI : 10.1109/TCSI.2017.2747087.A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI
2018. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018. DOI : 10.1109/ISCAS.2018.8351043.Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things
Proceedings Of The IEEE. 2018. DOI : 10.1109/Jproc.2017.2780172.Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster
Ieee Micro. 2017. DOI : 10.1109/MM.2017.3711645.Blind detection of polar codes
2017. IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, October 3-5, 2017. DOI : 10.1109/SiPS.2017.8109977.PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2017. DOI : 10.1109/JETCAS.2017.2745704.High-Speed Wireline Link Design
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7758.Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. DOI : 10.1109/TCSI.2017.2698138.Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes
ACM Transactions on Design Automation of Electronic Systems. 2017. DOI : 10.1145/3054744.Polar codes and APSK modulation - Just good friends
Information Theory and Applications Workshop (ITA), San Diego, CA, USA, Feb. 12-17, 2017.Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders
2017. IEEE Wireless Communications and Networking Conference (WCNC), San Francisco, CA, USA, Mar. 2017. p. 1-6. DOI : 10.1109/WCNCW.2017.7919106.An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2017. DOI : 10.1007/s11265-015-1086-1.A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code
2016. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2016. p. 1194-1198. DOI : 10.1109/ACSSC.2016.7869561.Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments
Ieee Transactions On Antennas And Propagation. 2016. DOI : 10.1109/Tap.2016.2624138.High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding
2016. IEEE Conference on Standards for Communications and Networking (CSCN), Berlin, GERMANY, OCT 31-NOV 02, 2016.Hardware Decoders for Polar Codes: An Overview
2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 149-152.Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016. DOI : 10.1145/2897937.2696095.A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS
2016. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016. p. 309-312.Approximate Computing for Unreliable Silicon
2016. 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design
2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 1006-1009.Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
Acm Transactions On Design Automation Of Electronic Systems. 2016. DOI : 10.1145/2890498.Microarchitectural Low-Power Design Techniques for Embedded Microprocessors
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7168.Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7297.Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2016. DOI : 10.1007/s11265-015-1003-7.Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS
Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2016.2537931.Modulation, Coding, and Receiver Design for Gigabit mmWave Communication
Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7111.A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination
2016. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016. p. 2667-2670.193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
2016. 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), Yokohama, Japan, April 20-22, 2016. DOI : 10.1109/CoolChips.2016.7503670.Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs
Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2015.2512706.Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers
2016. 17th IEEE International workshop on Signal Processing Advances in Wireless Communications, Edinburgh, Scotland, UK, July 3-6, 2016.DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment
2016. 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016. p. 261-264.Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency
2016. IEEE 83rd Vehicular Technology Conference, Nanjing, China, 15-18 May.Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016. p. 13:1-13:6. DOI : 10.1145/2897937.2898095.Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices
2016. Design, Automation and Test in Europe Conference (DATE '16), Dresden, Germany, March 14-18, 2016. p. 838-841.Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. DOI : 10.1109/TVLSI.2015.2394459.Method and apparatus for low complexity spectral analysis of bio-signals
US9760536 ; US2015220486 ; EP2884884 ; WO2014027329 . 2015.Power analysis and optimization of on-board processing for the EFM32 microprocessor
2015Automated Performance Characterization of Dynamic Clock Adjustment Techniques on an OpenRISC ISS
2015An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes
2015. 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015.Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems
2015. 2015 22nd IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, December 06-09, 2015. p. 637-640.Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication
2015. 49th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 8-11, 2015.A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm
2015. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, November 9-11, 2015. p. 193-196.An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity
Ieee Journal Of Solid-State Circuits. 2015. DOI : 10.1109/Jssc.2015.2417802.LLR-Based Successive Cancellation List Decoding of Polar Codes
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2439211.Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation
2015. 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, Hangzhou, China, 22-25 06 2015. p. 407-408. DOI : 10.1145/2746285.2764932.Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression
EURASIP Journal on Wireless Communications and Networking. 2015. DOI : 10.1186/s13638-015-0350-1.Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication
2015. Midwest Symposium on Circuits and Systems, Fort Collins, Colorado, USA, August 2-5, 2015.Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors
Nanotera Annual Meeting 2015, Bern, Switzerland, May 5, 2015.Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
Acm Transactions On Embedded Computing Systems. 2015. DOI : 10.1145/2656207.Approximate Computing With Unreliable Dynamic Memories
2015. International New Circuits And Systems Conference (NEWCAS), Grenoble, France, June 7-10, 2015.Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories
2015. DATE 2015, Grenoble, France, March 9-13, 2015.Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications
2015. Design Automation Conference (DAC'15), San Francisco, California, USA, June 7-11, 2015. p. 1-6. DOI : 10.1145/2744769.2744871.An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop
2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7169017.Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder
2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7168911.Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment
2015. The Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2015.Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing
WO2013136259 ; WO2013136259 . 2014.Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform
2014Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes
2014. IEEE International Symposium on Information Theory (ISIT), Honolulu, HI, JUN 29-JUL 04, 2014. p. 2977-2981.Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams
University Booth at DATE 2014, Dresden, Germany, March 24-28, 2014.Energy Efficiency through Significance-Based Computing
Computer. 2014. DOI : 10.1109/MC.2014.182.Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers
2014. [IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)', u'IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)'].Enseignement & Phd
Enseignement
Electrical and Electronics Engineering
Programmes doctoraux
Doctorants
Kostak Duygu, Kristensen Andreas Toftegaard, La Rosa Roberto, Li Sitian, Pekçokgüler Naci, Schumacher Adrian, Tapparel Joachim Tobias, Yigit Halil Andac,A dirigé les thèses EPFL de
Afisiadis Orion , Akkaya Ayça , Amarù Luca Gaetano , Balatsoukas Stimming Alexios Konstantinos , Bonetti Andrea , Constantin Jeremy Hugues-Felix , Dogan Ahmed Yasir , Ghanaatian Jahromi Reza , Meinerzhagen Pascal Andreas , Müller Thomas Christoph , Narinx Jonathan Emmanuel D , Preyss Nicholas Alexander , Senning Carl Christian Sten Dominic , Yousefbeiki Mohsen , Yüksel Hazar , Çelik Firat ,Cours
Digital systems design
Le cours permet d'acquérir des connaissances de base sur les méthodologies et les outils pour la conception, l'optimisation et la vérification de composants et systèmes matériels digitaux. Le langage VHDL est utilisé pour décrire une architecture matérielle qui sera ensuite synthétisée sur FPGA.TP en technologies de l'information
Se familiariser avec les aspects pratiques des disciplines de l'orientation «Technologies de l'information»Fundamentals of VLSI design
Le cours présente les principes fondamentaux des circuits intégrés numériques et les aspects technologiques du point de vue des concepteurs. Il se concentre principalement sur le niveau des transistors, mais discute également de l'extension aux grandes conceptions numériques semi-personnalisées.Advanced VLSI design
Dans ce cours basé sur un projet, les étudiants acquièrent une expérience pratique de la conception de circuits VLSI numériques entièrement personnalisés en logique dynamique. Ils apprennent à réaliser la conception et l'optimisation au niveau du transistor, y compris la logique et le clock tree.Wireless receivers: algorithms and architectures
Les étudiants apprendront les principes de base des systèmes de communication sans fil, y compris les schémas de transmission et de modulation ainsi que les composants et algorithmes de base d'un récepteur sans fil. Ils développent une compréhension des performances et des limites du canal sans fil.Advanced wireless receivers
Les étudiants étendent leurs connaissances sur les systèmes de communication sans fil à la communication à spectre étalé et aux systèmes multi-antennes. Ils apprennent également les concepts de base de la théorie de l'information, le codage des canaux et la modulation codée entrelacée par bits.Energy Autonomous Wireless Smart Systems
Introduction to Energy Autonomous Wireless Systems (D. Briand / 2h)
- Description of course organization and content
- Introduction to EAWS, building blocks, state of the art, applications, case studies
Energy sources and storage (D. Briand / 6h)
Working principles, technologies and comparison (efficiency, power density, potential applications) of energy sources and st