Andreas Peter Burg
andreas.burg@epfl.ch +41 21 693 69 24
EPFL STI IEL TCL
ELD 130 (Bâtiment ELD)
Station 11
CH-1015 Lausanne
Biography
Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006.
In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory.
In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor.
In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP).
Research interests and expertise
* Circuits and systems for telecommunications (wireless and wired)
* Prototyping and silicon implementation of new communication technologies
* Development of communication algorithms and optimization for hardware implementation
* Low-power VLSI signal processing for communications and other applications
* Digital integrated circuits
* Circuits for image and video processing
Publications Infoscience
Infoscience
R. Giterman; A. Bonetti; A. Burg; A. Teman : GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI; Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2019-12-01. DOI : 10.1109/TCSII.2019.2896164.
A. Burg; S. Mukhopdhyay; M. Ziegler : 2019 International Symposium on Low Power Electronics and Design; Ieee Design & Test. 2019-12-01. DOI : 10.1109/MDAT.2019.2941713.
M. Pons; C. T. Mueller; D. Ruffieux; J.-L. Nagel; S. Emery et al. : A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS. 2019-01-01. 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr 14-17, 2019.
E. V. Bravo; A. Bonetti; A. Burg : Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space. 2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019.
H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. : Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders; Ieee Transactions On Circuits And Systems I-Regular Papers. 2018-10-01. DOI : 10.1109/TCSI.2018.2803735.
A. Balatsoukas-Stimming; A. Burg : Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel; IEEE TRANSACTIONS ON COMMUNICATIONS. 2018. DOI : 10.1109/TCOMM.2017.2771243.
P. Giard; A. Burg : Fast-SSC-Flip Decoding of Polar Codes. 2018. DOI : 10.1109/WCNCW.2018.8369026.
R. Giterman; A. Fish; N. Geuli; E. Mentovich; A. Burg et al. : An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications; IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2018. DOI : 10.1109/JSSC.2018.2820145.
R. Ghanaatian; A. Balatsoukas-Stimming; T. Muller; M. Meidlinger; G. Matz et al. : A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing; IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2018. DOI : 10.1109/TVLSI.2017.2766925.
R. Giterman; A. Fish; A. Burg; A. Teman : A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI; IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. DOI : 10.1109/TCSI.2017.2747087.
A. Bonetti; J. Constantin; A. S. Teman; A. P. Burg : A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. 2018. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018.
A. Burg; A. Chattopadhyay; K.-Y. Lam : Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things; Proceedings Of The IEEE. 2018. DOI : 10.1109/Jproc.2017.2780172.
D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gurkaynak et al. : Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster; Ieee Micro. 2017. DOI : 10.1109/MM.2017.3711645.
P. Giard; A. K. Balatsoukas Stimming; A. P. Burg : Blind detection of polar codes. 2017. IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, October 3-5, 2017. DOI : 10.1109/SiPS.2017.8109977.
P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. Bonetti; C. Thibeault et al. : PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes; IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2017. DOI : 10.1109/JETCAS.2017.2745704.
A. Bonetti; A. S. Teman; P. Flatresse; A. P. Burg : Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters; IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. DOI : 10.1109/TCSI.2017.2698138.
A. Bonetti; N. A. Preyss; A. S. Teman; A. P. Burg : Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes; ACM Transactions on Design Automation of Electronic Systems. 2017. DOI : 10.1145/3054744.
N. A. Preyss; P. Giard; A. K. Balatsoukas Stimming; A. P. Burg : Polar codes and APSK modulation - Just good friends ; Information Theory and Applications Workshop (ITA), San Diego, CA, USA, Feb. 12-17, 2017.
A. K. Balatsoukas Stimming; P. Giard; A. P. Burg : Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. 2017. IEEE Wireless Communications and Networking Conference (WCNC), San Francisco, CA, USA, Mar. 2017. p. 1-6. DOI : 10.1109/WCNCW.2017.7919106.
J. Constantin; R. Houlmann; N. Preyss; N. Walenta; H. Zbinden et al. : An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2017. DOI : 10.1007/s11265-015-1086-1.
P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. P. Burg; C. Thibeault et al. : A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code. 2016. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2016. p. 1194-1198. DOI : 10.1109/ACSSC.2016.7869561.
M. Yousefbeiki; A. C. M. Austin; J. R. Mosig; A. Burg; J. Perruisseau-Carrier : Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments; Ieee Transactions On Antennas And Propagation. 2016. DOI : 10.1109/Tap.2016.2624138.
H. Yueksel; G. Cherubini; R. D. Cideciyan; S. Furrer; A. Burg et al. : High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding. 2016. IEEE Conference on Standards for Communications and Networking (CSCN), Berlin, GERMANY, OCT 31-NOV 02, 2016.
P. Giard; G. Sarkis; A. Balatsoukas-Stinning; Y. Fan; C.-Y. Tsui et al. : Hardware Decoders for Polar Codes: An Overview. 2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 149-152.
J. Constantin; A. Burg; Z. Wang; A. Chattopadhyay; G. Karakonstantis : Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance. 2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016. DOI : 10.1145/2897937.2696095.
H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. : A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS. 2016. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016. p. 309-312.
A. P. Burg : Approximate Computing for Unreliable Silicon. 2016. 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
R. Giterman; A. Teman; P. Meinerzhagen; A. Fish; A. Burg : A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design. 2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 1006-1009.
A. Teman; D. Rossi; P. Meinerzhagen; L. Benini; A. Burg : Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement; Acm Transactions On Design Automation Of Electronic Systems. 2016. DOI : 10.1145/2890498.
C. Senning; G. Karakonstantis; A. Burg : Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2016. DOI : 10.1007/s11265-015-1003-7.
O. Andersson; B. Mohammadi; P. Meinerzhagen; A. Burg; J. N. Rodrigues : Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS; Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2016.2537931.
R. Ghanaatian Jahromi; P. Whatmough; J. H.-F. Constantin; A. S. Teman; A. P. Burg : A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination. 2016. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016. p. 2667-2670.
D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gürkaynak et al. : 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. 2016. 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), Yokohama, Japan, April 20-22, 2016. DOI : 10.1109/CoolChips.2016.7503670.
N. Edri; P. Meinerzhagen; A. Teman; A. Burg; A. Fish : Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs; Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2015.2512706.
A. Austin; A. K. Balatsoukas Stimming; A. Burg : Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers. 2016. 17th IEEE International workshop on Signal Processing Advances in Wireless Communications, Edinburgh, Scotland, UK, July 3-6, 2016.
J. H.-F. Constantin; A. Bonetti; A. S. Teman; T. C. Müller; L. F. Schmid et al. : DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment. 2016. 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016. p. 261-264.
O. Afisiadis; A. C. M. Austin; A. K. Balatsoukas Stimming; A. Burg : Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency. 2016. IEEE 83rd Vehicular Technology Conference, Nanjing, China, 15-18 May.
J. H.-F. Constantin; Z. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg : Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance. 2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016. p. 13:1-13:6. DOI : 10.1145/2897937.2898095.
L. G. Duch; P. Garcia del Valle; S. Ganapathy; A. P. Burg; D. Atienza Alonso : Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices. 2016. Design, Automation and Test in Europe Conference (DATE '16), Dresden, Germany, March 14-18, 2016. p. 838-841.
R. Giterman; A. Teman; P. Meinerzhagen; L. Atias; A. Burg et al. : Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications; Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. DOI : 10.1109/TVLSI.2015.2394459.
G. Karakonstantis; A. Sankaranarayanan; A. Burg; S. Murali; D. Atienza Alonso ; Method and apparatus for low complexity spectral analysis of bio-signals. US9760536 ; US2015220486 ; EP2884884 ; WO2014027329 . 2015.
J. M. Wüthrich; A. K. Balatsoukas Stimming; A. P. Burg : An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes. 2015. 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015.
N. A. Preyss; A. Burg : Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems. 2015. 2015 22nd IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, December 06-09, 2015. p. 637-640.
N. Preyss; S. Rodriguez Egea; A. Burg : Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication. 2015. 49th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 8-11, 2015.
N. A. Preyss; C. C. S. D. Senning; A. P. Burg; W.-C. Liu; C.-Y. Liu et al. : A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm. 2015. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, November 9-11, 2015. p. 193-196.
H. Kroell; S. Zwicky; B. Weber; C. Roth; D. Tschopp et al. : An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity; Ieee Journal Of Solid-State Circuits. 2015. DOI : 10.1109/Jssc.2015.2417802.
A. Balatsoukas-Stimming; M. B. Parizi; A. Burg : LLR-Based Successive Cancellation List Decoding of Polar Codes; Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2439211.
A. Austin; O. Afisiadis; A. Balatsoukas-Stimming; A. Burg : Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation. 2015. 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, Hangzhou, China, 22-25 06 2015. p. 407-408. DOI : 10.1145/2746285.2764932.
A. Balatsoukas-Stimming; A. Austin; P. Belanovic; A. Burg : Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression; EURASIP Journal on Wireless Communications and Networking. 2015. DOI : 10.1186/s13638-015-0350-1.
N. A. Preyss; L. Koester; A. P. Burg : Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication. 2015. Midwest Symposium on Circuits and Systems, Fort Collins, Colorado, USA, August 2-5, 2015.
A. Bonetti; J. H.-F. Constantin; A. S. Teman; A. P. Burg : Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors ; Nanotera Annual Meeting 2015, Bern, Switzerland, May 5, 2015.
M. Owaida; G. Falcao; J. Andrade; C. Antonopoulos; N. Bellas et al. : Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs; Acm Transactions On Embedded Computing Systems. 2015. DOI : 10.1145/2656207.
S. Ganapathy; A. S. Teman; R. Giterman; A. P. Burg; G. Karakonstantis : Approximate Computing With Unreliable Dynamic Memories. 2015. International New Circuits And Systems Conference (NEWCAS), Grenoble, France, June 7-10, 2015.
A. S. Teman; G. Karakonstantis; A. P. Burg; R. Giterman; P. A. Meinerzhagen : Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories. 2015. DATE 2015, Grenoble, France, March 9-13, 2015.
S. Ganapathy; G. Karakonstantis; A. S. Teman; A. P. Burg : Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications. 2015. Design Automation Conference (DAC'15), San Francisco, California, USA, June 7-11, 2015. p. 1-6. DOI : 10.1145/2744769.2744871.
A. Bonetti; A. S. Teman; A. P. Burg : An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop. 2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7169017.
P. A. Meinerzhagen; A. Bonetti; G. Karakonstantis; C. Roth; F. K. Gürkaynak et al. : Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder. 2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7168911.
J. H.-F. Constantin; L. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg : Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment. 2015. The Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2015.
A. Y. Dogan; J. Constantin; A. Burg; D. Atienza Alonso ; Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing. WO2013136259 ; WO2013136259 . 2014.
A. Balatsoukas-Stimming; G. Karakonstantis; A. Burg : Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes. 2014. IEEE International Symposium on Information Theory (ISIT), Honolulu, HI, JUN 29-JUL 04, 2014. p. 2977-2981.
L. Amarù; A. Balatsoukas Stimming; P.-E. Gaillardon; A. Burg; G. De Micheli : Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams ; University Booth at DATE 2014, Dresden, Germany, March 24-28, 2014.
D. S. Nikolopoulos; H. Vandierendonck; N. Bellas; C. D. Antonopoulos; S. Lalis et al. : Energy Efficiency through Significance-Based Computing; Computer. 2014.
C. Senning; M. Mendicute; A. Burg : Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers. 2014. [IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)', u'IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)'].
G. Kail; P. Maechler; N. Preyss; A. Burg : Robust Asynchronous Indoor Localization Using Led Lighting. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
N. A. Preyss; R. Pantic; A. P. Burg : Correlation Based Phase Noise Compensation in 60 GHz Wireless Systems. 2014. 2014 IEEE 28-th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December, 3-5, 2014.
R. Giterman; A. Teman; P. Meinerzhagen; A. Burg; A. Fish : 4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. 2014. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1-5 June 2014. p. 2177-2180. DOI : 10.1109/ISCAS.2014.6865600.
S. Ganapathy; G. Karakonstantis; R. Canal; A. P. Burg : Variability-Aware Design Space Exploration of Embedded Memories. 2014. 28th IEEE Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December 3-5, 2014.
A. Balatsoukas-Stimming; A. J. Raymond; W. J. Gross; A. Burg : Hardware Architecture for List Successive Cancellation Decoding of Polar Codes; Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2327336.
R. Braojos Lopez; I. Beretta; J. H.-F. Constantin; A. P. Burg; D. Atienza Alonso : A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead. 2014. The 12th IEEE International Conference on Embedded and Ubiquitous Computing, Milan, 25-29.08.2014.
I. Kazi; P. Meinerzhagen; P.-E. Gaillardon; D. Sacchetto; Y. Leblebici et al. : Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design; IEEE Transactions on Circuits and Systems Part 1 Regular Papers. 2014. DOI : 10.1109/TCSI.2014.2334891.
V. Camus; G. Karakonstantis; J. Schlachter; A. P. Burg; C. Enz : Cross-Layer Inexact Design for Low-Power Applications ; NanoTera Annual Meeting, Lausanne, Switzerland.
A. Teman; P. Meinerzhagen; R. Giterman; A. Fish; A. Burg : Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM; Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2305016.
A. Balatsoukas-Stimming; M. Bastani Parizi; A. P. Burg : LLR-based Successive Cancellation List Decoding of Polar Codes. 2014. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2014), Florence, Italy, May 4-9, 2014.
A. Balatsoukas-Stimming; A. P. Burg : Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage; IEEE Communications Letters. 2014. DOI : 10.1109/Lcomm.2014.030714.132830.
A. Balatsoukas-Stimming; G. Karakonstantis; A. P. Burg : Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes. 2014. IEEE International Symposium on Information Theory, Honolulu, Hawaii, USA, June 29 - July 4, 2014.
M. Yousefbeiki; P. Belanovic; A. P. Burg; J. Perruisseau-Carrier : True MIMO transmission using a single RF-chain and antenna: recent developments. 2014. Eucap 2014, 8th European Conf. on Antennas and Prop., The Hague, Netherlands, 2014.
C. Senning; L. Bruderer; J. Hunziker; A. Burg : A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s; IEEE Transactions on Circuits and Systems I. 2014. DOI : 10.1109/TCSI.2013.2295027.
N. Walenta; A. P. Burg; D. Caselunghe; J. H.-F. Constantin; N. Gisin et al. : A Fast and Versatile Quantum Key Distribution System with Hardware Key Distillation and Wavelength Multiplexing; New Journal of Physics. 2014. DOI : 10.1088/1367-2630/16/1/013047.
G. Karakonstantis; A. Sankaranarayanan; M. M. S. Aly; D. Atienza Alonso; A. P. Burg : A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability. 2014. Design Automation & Test in Europe (DATE), Dresden, Germany.
L. Amarù; P.-E. Gaillardon; A. Burg; G. De Micheli : Data Compression via Logic Synthesis. 2014. 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, January 20-23, 2014. p. 628-633. DOI : 10.1109/ASPDAC.2014.6742961.
A. Burg; A. Teman; A. Fish; P. Meinerzhagen : Impact of body biasing on the retention time of gain-cell memories; The Journal of Engineering. 2013. DOI : 10.1049/joe.2013.0057.
C. C. S. D. Senning; A. P. Burg : Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems. 2013. 2013 IEEE International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11, 2013.
P. Belanovic; A. Balatsoukas-Stimming; A. Burg : A Multipurpose Testbed for Full-Duplex Wireless Communications ; International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11 2013.
A. Balatsoukas-Stimming; P. Belanovic; K. Alexandris; A. Burg : On Self-interference Suppression Methods for Low-complexity Full-duplex MIMO. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 3-6, 2013.
J. H.-F. Constantin; A. Dogan; O. Andersson; P. A. Meinerzhagen; J. Rodrigues et al. : An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing; VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; Springer, 2013. p. 88-106.
R. Cojbasic; Ö. Cogal; P. A. Meinerzhagen; C. C. S. D. Senning; C. J. Slater et al. : FireBird: PowerPC e200 Based SoC for High Temperature Operation. 2013. IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, USA, September 23-25, 2013.
S. Zwicky; C. Benkeser; A. P. Burg; Q. Huang : Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications. 2013. 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vancouver, Canada, May 26-31, 2013.
I. Kazi; P. A. Meinerzhagen; P.-E. J. M. Gaillardon; D. Sacchetto; A. P. Burg et al. : A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write. 2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013.
A. Balatsoukas Stimming; N. Preyss; A. Cevrero; A. Burg; C. Roth : A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad. 2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013. DOI : 10.1109/NEWCAS.2013.6573590.
P. A. Meinerzhagen; A. Teman; R. Giterman; A. P. Burg; A. Fish : Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling; Journal of Low Power Electronics and Applications. 2013. DOI : 10.3390/jlpea3020054.
A. Cevrero; N. Evmorfopoulos; C. Antoniadis; P. Ienne; Y. Leblebici et al. : Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory. 2013. Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, March 18-22, 2013.
A. P. Burg : Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems ; Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013.
A. Y. Dogan; R. Braojos Lopez; J. H.-F. Constantin; G. Ansaloni; A. P. Burg et al. : Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms. 2013. The Design, Automation and Test in Europe (DATE), 2013, Grenoble, France.
A. Y. Dogan; J. H.-F. Constantin; D. Atienza Alonso; A. P. Burg; L. Benini : Low-power processor architecture exploration for online biomedical signal analysis; Circuits, Devices & Systems, IET. 2012. DOI : 10.1049/iet-cds.2012.0011.
P. Maechler; C. Studer; D. Bellasi; A. Maleki; A. P. Burg et al. : VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing; IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2012. DOI : 10.1109/JETCAS.2012.2214636.
S. Belfanti; C. Benkeser; K. Badawi; Q. Huang; A. P. Burg : Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture. 2012. IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, CA, USA, October 7-10, 2012.
H. Kröll; S. Zwicky; C. Benkeser; Q. Huang; A. P. Burg : Low-complexity Frequency Synchronization for GSM Systems: Algorithms and Implementation. 2012. International Conference on Ultra Modern Telecommunications (ICUMT), St. Petersburg, Russia, October 3-5, 2012.
C. Roth; C. Benkeser; C. Studer; G. Karakonstantis; A. P. Burg : Data Mapping for Unreliable Memories. 2012. 50th Annual Allerton Conference on Communication, Control, and Computing, October, 1-5, 2012.
A. Teman; P. A. Meinerzhagen; A. P. Burg; A. Fish : Review and Classification of Gain Cell eDRAM Implementations; IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI). 2012.
G. Falcao Fernandes; D. Novo Bruna; M. Purnaprajna; N. Bellas; C. Antonopoulos et al. : Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case. 2012. IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012.
