Ayatallah Elakhras
EPFL IC IINFCOM LAP
INF 134 (Bâtiment INF)
Station 14
1015 Lausanne
Web site: Web site: https://lap.epfl.ch/
Fields of expertise
- High-Level Synthesis
- Dataflow Architecture
- Compilers
Biography
Ayatallah is a Ph.D. student in the Processor Architecture Laboratory, advised by Professor Paolo Ienne. Between October 2023 and March 2024, she did an internship at AMD in the Research and Advanced Development team, under the supervision of Dr. Kristof Denolf. She received a B.Sc. degree in Computer Engineering from the American University in Cairo, Egypt in 2020 and started her Ph.D. in the same year.Her research interests include dataflow architecture, electronic design automation, and compilers. Her current research focuses on optimizing dataflow circuits generated for dynamically scheduled high-level synthesis.
Awards
Google PhD Fellowship
EPFL EDIC Doctoral Fellowship
Publications
Selected publications
| Ayatallah Elakhras*, Jiahui Xu*, Martin Erhart, Paolo Ienne, and Lana Josipović. In Proceedings of the Intl. Conference on Architectural Support for Programming Languages and Operating Systems, to appear. |
ElasticMiter: Formally Verified Dataflow Circuit Rewrites. |
| Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. In Proceedings of the 32nd ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays. |
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. |
| Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays. |
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. |
| Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. In Proceedings of the 32nd International Conference on Field‐Programmable Logic and Applications. |
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. |