Babak Falsafi

Biography and current work

Biography

Babak is a Professor in the School of Computer and Communication Sciences and the founding director of the EcoCloud research center pioneering future energy-efficient and environmentally-friendly cloud technologies at EPFL. He has made numerous contributions to computer system design and evaluation including a scalable multiprocessor architecture which was prototyped by Sun Microsystems (now Oracle), snoop filters and temporal stream prefetchers that are incorporated into IBM BlueGene/P and BlueGene/Q, and computer system simulation sampling methodologies that have been in use by AMD and HP for research and product development. His most notable contribution has been to be first to show that contrary to conventional wisdom, multiprocessor memory programming models -- known as memory consistency models -- prevalent in all modern systems are neither necessary nor sufficient to achieve high performance. He is a recipient of an NSF CAREER award, IBM Faculty Partnership Awards, and an Alfred P. Sloan Research Fellowship. He is a fellow of IEEE and ACM.

NEWS

CloudSuite 3.0 is now released (with tutorials at EuroSys and HiPEAC in 2016). CloudSuite 3.0 is Docker-ready and integrated into Google PerfKit.

Cavium ThunderX, a recent ARM-based server processor, is the first scale-out processor which is workload-optimized based on our work in "Clearing the Clouds" and the first version of CloudSuite. See this article in EETimes from EEMBC and Cavium.

The EuroCloud Server project has been hailed as a "flagship" project to drive innovation in datacenter design by EU. See the ACM Tech report snippet.

RESEARCH

Babak's research and educational activities primarily center around architectural innovation to address four emerging challenges in the design and performance-scalability of future computer systems: (1) the “programming wall”, due to the emergence of multiprocessor chips as the hardware pillars for future IT infrastructure and the lack of commodity parallel software, (2) the “memory wall”, due to the ever-growing gap between processor and memory performance, (3) the “technology wall”, due to the exponential increase in system power consumption and the dramatic reduction in circuit reliability and testability in emerging CMOS fabrication processes, and (4) the “simulation wall”, due to the increase in hardware and software complexity necessitating detailed modeling and representative measurement. He investigates techniques to address these challenges in the context of the following projects:

• CloudSuite: A Benchmark Suite for Scale-Out Workloads
  
• SimFlex/ProtoFlex: Fast, Full-System Scalable Multiprocessor Simulation/Emulation
  
• Scale-Out NUMA: Rack-Scale Computer Architecture
  
• VISA: Server Processors for the Dark Silicon Era
  
  
  

Selected Talks

Public Clouds will Subsume (Most of) HPC
HPC Summit,
May 2017, PDF.

Memory-Centric Server Architecture
Talks at Columbia, Edinburgh and HKUST,
2016, PDF.

Big Data & Dark Silicon: Taming Two IT Trends on a Collision Course
HiPEAC CSW & IEEE CloudNet Keynotes,
October 2014, PDF.

Reliability in the Dark Silicon Era
IOLTS 2011 Keynote,
July 2011, PDF.

Dark Silicon & Its Implications on Server Chip Design
Microsoft Research,
November 2010, PDF, Video.

TRUSS: Reliable, Scalable Server Architecture
Georgia Institute of Technology, College of Computing Colloquia,
April 2006, PDF.

Temporal Memory Streaming
University of Texas, Computer Science Department Colloquia,
December 2005, PDF.

Transactional Execution: Wait-Free Hardware Memory Ordering
Dagstuhl Seminar on "Hardware and Software Consistency
Models: Programmability and Performance",
October 2003, PDF.