Farzan Jazaeri

ELB 336 (Bâtiment ELB)
Station 11
CH-1015 Lausanne


Site web: https://iclab.epfl.ch
Unité: ICLAB

Données administratives

Modeling and fabrication of nanowire junctionless FETs and Vertical Slit FETs: To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap. In this context, the junctionless FET and vertical slit FETs are parts of these attempts. They are new emerging devices that can potentially withstand the downscaling of CMOS technology as they still have an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. In this project, we focused on the physics and modeling of nanoscale junctionless nanowire FETs and VeSFETs and development of a new model (EPFL-JL), detailed in [1]. This includes modeling short-channel effects and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off-state currents.
[1] Farzan Jazaeri and Jean-Michel Sallese. Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors. Cambridge University Press, 2018.