Biographie

Farzan Jazaeri received his M.Sc. degree in 2009 from University of Tehran and his Ph.D. in electronic engineering from EPFL in 2015. He has been serving as Research Scientist at EPFL since 2015 and Senior RD Semiconductor Device Engineer in the Swatch Company since 2019.

He is a recipient of the 2018 Electron Devices Society George E. Smith Award, the best talk award from MIXDES 2019 and the best paper awards from ESSDERC2018 and ESSDERC2019, and several other academic awards. He is also awarded an advanced Swiss National Science Foundation grant for two years fellowship in MIT and NASA. His doctoral thesis was recognized to be eligible for the IBM award in 2017. Dr. Jazaeri is currently research scientist and project leader in high level of international scientific collaborative activities at EPFL. His research activities on solid-state physics are focused on creation of the cryogenic temperature infrastructure necessary to operate the qubits for quantum computations(MOSQUITO), radiation-induced damages in advanced devices for the future high energy physics experiments at CERN (GigaRadMOST), Pinned Photodiodes for CIS, and modeling and characterization AlGaN-GaN heterostructure in collaboration with IMEC. Together with Dr. Sallese, he is the lead developer of EPFL HEMT MODEL for GaN HEMTs. He fully developed a new model (EPFL-JL Model) for the so-called nanowire FETs and was invited by Cambridge University Press to write a book on junctionless nanowire FETs, emerging nanoelectronic devices, already published since 2018. He serves as lead editor and reviewer for several scientific journals. He has been an invited keynote speaker at several international conferences and events. He is invited to MIXDES 2019 as a keynote speaker to address quantum bits and quantum computing architecture.
From Jun 2009 to February 2010, he worked on designing and implementing SD/HD broadcast systems with SAMIM-RAYANEH Co., Tehran, Iran. 
Between March 2010 and November 2011 he worked as a SCADA expert in Tehran Regional Electric Co. (TREC), Tehran, Iran. From September 2010 to December 2011, he continued his research activities in nano-electronics in Tehran, Iran. In December 2011, he joined to Electron Device Modelling and Technology Lab (EDLab) and pursued his Ph.D. degree at EPFL. In 2015, he received his Ph.D. from Microsystems and Microelectronics department, Integrated Systems Laboratory (STI/IC) at EPFL, Lausanne, Switzerland. 

Travail en cours

My current research activities on solid state physics are focused around different aspects of semiconductor physics, ranging from materials science to quantum physics, to different applications. My attention is not only limited to the lowest level technology, includes also physics modeling of electron devices. I have been devoting much effort to these subjects, both at the level of devices and modeling and characterization of nanoscale FETs. Within this context, I pursue different research lines and following interwoven focal research activities exist:
GigaRadMOST: Since December 2015, I have been supervising a PhD student (Chunmin Zhang) for modeling radiation effects on nanoscale MOSFETs. The objective of this project is to understand and accurately model the effect of accumulated dose on advanced FETs. The Large Hadron Collider (LHC) at CERN is the world's largest and most powerful scientific facility ever built. To promote the scientific progress, it will need a major upgrade around 2020 for a higher luminosity. The HL-LHC will rely on a number of key innovative technologies including much more radiation-tolerant silicon tracking systems with higher granularity and higher bandwidth. Therefore, we are investigating the use of a 28 nm bulk CMOS process for both a higher radiation tolerance and higher bandwidth. The effects of the charge buildup related to the gate oxide and the STI oxide remain unclear in deep submicron MOSFETs. This project, funded by the Swiss National Science Foundation (SNSF) under grant number 200021 160185, is a collaboration between ScalTech28 project and Microelectronic Group, Istituto Nazionale di Fisica Nucleare (INFN), EP-ESE Group, CERN, University of Udine, and University of Milano-Bicocca.

MOS-Quito: Since April 2016, I have been supervising a PhD student (Arnout Beckers) for MOSFET modeling at cryogenic temperatures down to 20mk for quantum computing. A quantum computer relies on a new processing core, based on quantum bits (qubits) storing the information in entanglements between different qubits. To keep this qubit decoherence at a minimum, the qubits are operated at cryogenic temperatures, which rings at least the thermal noise as low as possible. To design the cryogenic control circuits, a full edged cryogenic MOS transistor model is essential, in order to meet the specifications at cryogenic temperature. This project has received funding from the European Union's Horizon 2020 Research and Innovation Programme under grant agreement No. 688539 MOSQuito. Its main objective is the creation of the classical cryogenic temperature (down to 20mK) infrastructure necessary to operate the proposed qubits for quantum computations. This project is funded by the European union in collaboration with: CEA-LETI, London's Global University, University of Cambridge, University of Copenhagen, Technical Research Centre of Finland, and IMM.

Pinned-photodiode (PPD) for CMOS Image Sensors: the task of guidance a PhD student (Raffaele Capoccia) for modeling of PPDs in image sensors. The continuous improvements of CMOS image sensors (CIS) in terms of quantum efficiency, speed, and resolution brought this low-cost device into high-performance applications, replacing progressively the charge coupled devices (CCDs). At present, the pinned photodiodes (PPDs) are popularly used in photon-to-electricity conversion process. In this project, we propose to develop a precise physics-based model for the evaluation of the full well capacity of pinned photodiode (PPD) CMOS image sensors to capture the experimental measurement results which would enable to analyze the light response characteristics of pinned-photodiodes.

Negative capacitance FETs: Since December 2015, I have been collaborating with Nano-Lab at EPFL and have been guiding a PhD student (Ali Saeidi) for modeling and fabrication negative capacitance FETs. The limit of the thermal swing is a fundamental limit that cannot be defeated in conventional FETs. However, an average subthreshold swing smaller than its theoretical limit of MOSFET would enable the scaling of the supply voltage, reducing the power dissipation. Within this context, negative capacitance in ferroelectric material i.e. PZT, could provide a solution in FETs. In this project, we propose to experimentally investigate the impact of the ferroelectric negative capacitance on DC electrical behavior in advanced FETs, i.e. commercial MOSFETs fabricated in 28nm CMOStechnology and also tunnel FETs. For the first time, a non-hysteretic switch configuration in our fabricated MOSFETs are achieved. This project is funded by the Swiss National Science Foundation (SNSF) under grant number 149495.

Modeling and Microfabrication of GaN HEMTs: Recently, HEMTs have attracted attention due to their ability to operate at higher frequencies than regular transistors (i.e. MOSFETs), up to millimeter wave frequencies for high performance and RF applications. The focus of the work in this project is to develop a charge-based EPFL HEMT Model, predicting the electrical behavior of GaN HEMTs, fabricated by IMEC. The core equations of the intrinsic model are developed by Electron Device Lab at EPFL, while IMEC will develop a parasitic network for such devices. The EPFL HEMT Model is a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based  and the central concept is based on the linear approximation of the channel charge density with respect to the surface potential, leading to explicit and continuous expressions for charges and current in all the regions of operation, including subthreshold. In addition, an effective circuit design methodology based on the pinchoff surface potential, the pinchoff voltage and the key concept of inversion coefficient (IC) is proposed, likewise for silicon MOSFET circuits. The EPFL-HEMT model has been developed by EDLAB, École Polytechnique Fédérale  de Lausanne,(EPFL), Lausanne, Switzerland in cooperation with Amirkabir  University of Technology, Technical University of Crete(TUC), Chania, Crete, Greece, and IMEC.
Modeling and fabrication of nanowire junctionless FETs and Vertical Slit FETs: To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap. In this context, the junctionless FET and vertical slit FETs are parts of these attempts. They are new emerging devices that can potentially withstand the downscaling of CMOS technology as they still have an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. In this project, we focused on the physics and modeling of nanoscale junctionless nanowire FETs and VeSFETs and development of a new model (EPFL-JL), detailed in [1]. This includes modeling short-channel effects and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off-state currents.
[1] Farzan Jazaeri and Jean-Michel Sallese. Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors. Cambridge University Press, 2018.