Farzan Jazaeri was born in Tehran and received his M.Sc. degrees in Electrical and Electronics Engineering in 2009 from University of Tehran, Iran. From Jun 2009 to February 2010, he worked on designing and implementing SD/HD broadcast systems with SAMIM-RAYANEH Co., Tehran, Iran. Between March 2010 and November 2011 he worked as a SCADA expert in Tehran Regional Electric Co. (TREC), Tehran, Iran. From September 2010 to December 2011, he continued his research activities in nano-electronics in Tehran, Iran. In December 2011, he joined to Electron Device Modelling and Technology Lab (EDLab) and pursued his Ph.D. degree at EPFL. In 2015, he received his Ph.D. from Microsystems and Microelectronics department, Integrated Systems Laboratory (STI/IC) at EPFL, Lausanne, Switzerland.
He is currently a scientist in EPFL with research activities on modeling and characterization of nuclear radiation damage in advanced semiconductor devices (28 nm), mainly for high energy physics application at CERN and also CMOS device modeling and characterization at cryogenic temperatures (20 mK) for quantum computations. His technical interests and expertise are particular in semiconductor devices and physics, with a special interest for modeling, fabrication and characterization advanced field effect transistors and power semiconductor devices.
Together with Dr. Sallese, he is the developer of a new model (EPFL-JL model) for the so-called junctionless nanowire FETs and the author of an invited book on junctionless nanowire FETs, published by Cambridge University Press in 2017. He serves as lead editor and reviewer for several scientific journals.
working on modeling of junctionless multiple gate devices (nano-wires, JLDGMOSFETs and VeSFETs).
December 2011- December 2015: Ph.D., Microsystems and Microelectronics, Electrical engineering, EPFL, Lausanne, Switzerland.Thesis: Modeling of junctionless nanowire and double-gate FETs, multiple gate transistors and VeSFETs.
Fall 2006-Jan 2009: M.Sc., Circuits and Systems, Electronics, Electrical Engineering, University of Tehran, Iran.Thesis: Design of low-power and high performance integrated circuits
Fall 2001-2006: B.Sc., Electronics, Electrical Engineering, K.N.Toosi University of Technology, Tehran, Iran.Thesis: Analysis and design antennas and impedance matching circuits in submillimeter wave detectors using Josephson fluxonic diode.
Skills and Experiences
Device measurements, characterization, and parameter extraction:
Device design and TCAD: Sentaurus Device simulation, Silvaco, LEdit,
PiscesIIB, Mdraw, Dessis
Extensive skills in mathematics, physics and computational methods
IC design: Spice, Verilog
Algorithm Development Environments: MATLAB/Simulink, C
Conformal mapping and Extensive skills in partial and ordinary differential
Cleanroom Fabrication Process: Photolithography (Layout design,
Mask fabrication) deposition process, cleaning, etching process (Dry
Extensive experience in the area of FPGA-based hardware implementation.
Physics-based modeling, cleanroom fabrication, optimization, and characterization of advanced semiconductor devices
Power semiconductor devices i.e. JFET, HEMT, IGBT, nanostructured power devices, and wide band-gap devices.
Modeling nanoscale semiconductor devices operating at cryogenic temperature (down to 20mK) and radiation damages and total ionizing dose effects in integrated circuits
Optical MEMS and Micro-Optics, November 2014,(PhD)
Nanoscale MOS transistors: semi-classical modeling and applications, May 2013 (PhD)
Beyond CMOS devices, September 2012 (PhD)
Modeling micro/nano-field effect electron devices, August 2012 (PhD)
Integrated circuits technology, December, 2012 (PhD)
Modeling of emerging electron devices, December, 2012 (PhD)
Quantum Electronics and solid state, Fall 2010 (PhD)
Nano-Electronics, Fall 2010 (PhD)
Superconductivity, Fall 2010 (PhD)
Nano-Organics, Spring 2011(PhD)
Advanced Semiconductor Devices, Fall 2006 (M.Sc)
Semiconductor Devices Fabrication, Fall 2006 (M.Sc)
Nano Devices and their integration, Spring 2007 (M.Sc)
Low Power IC Design, Spring 2007 (M.Sc)
Silicon on Insulator (SOI) devices and circuits, Fall 2007 (M.Sc)
Solid state Physics, Fall 2007 (M.Sc)
Optoelectronic, Fall, 2007 (M.Sc)
Analog IC Design Fall, 2006 (M.Sc)
Physics-based modeling, characterization, and microfabrication of: (A) InGaAs HEMT devices in collaboration with IMEC, (B) Power semiconductor devices: JFET, HEMT nanowire FETs in collaboration with EDLAB, EPFL and university of Crete, (C) Nano-scale MOS transistors for high dose radiation particle physics experiments (GigaRadMOST and ScalTech28 projects), (D) Nano-scale MOS transistors at cryogenic temperatures, down to 20mK, for efficient qubit control in quantum computing (MOS-Quito Project), (F) Negative gate capacitance MOSFET and Tunnel FET in collaboration with Nanolab at EPFL.
Physical modeling of advanced semiconductor devices (Nanowire
and Multigates FETs)
Device optimization, characterization, and microfabrication
EPFL-JL- MODEL: Spice-level implementation of the EPFL Junctionless
Process and device simulation
Cleanroom fabrication process of micro-electronic devices.
Performance estimation of digital circuits using circuit simulators and comparison different proposed low-power logic styles.
Advanced MOSFET, nano scale SOI and FED devices modeling.
Using nano scale Field Effect Diode in ultra-Low-Power and high performance digital and analog designs (Variable Gain Amplifiers in AGC systems).
High performance and Low-Power of Double Edge Triggered Flip-Flops based on nano scale FinFET technologies.
Advanced MOSFET I-V Modeling.
Standard cell layout design and characterization.
Modification gate leakage model parameters of Predictive Technology Models (PTMs).
Submillimeter wave detection using Josephson fluxonic diode.
Implementing of DCT, DST and Gabor transformation on Programmable Function Arrays.
Verilog modeling of digital filters and FFT engines.
Worked on Controller Area Network (CAN).
MATLAB and Simulink system level modeling and computer simulations.
Analysis and measurement of signal distortion in RF application.
Mapping of DSP algorithms on Field Programmable Function Arrays.
Designing Patch and dipolar Antennas & impedance matching circuits design based on superconductor antennas.
"Nanowire Junctionless FETs," EDMI Research Day, EPFL, 2015.
"Nanowire Junctionless FETs: EPFL JL Model" EDMI Research Day, EPFL, 2016.
"Overview of Beyond CMOS Devices," IEEE University of Tehran Student Branch, 2017.
"Overview of Beyond CMOS Devices," Amirkabir University of Technology, 2017.
"Creative Problem Solving in Science and Engineering," Brain Engineering Research Center, Institute for Research in Fundamental Sciences (IPM), Tehran, 2017.
"Nanowire junctionless Field Effect Transistors," K.N. Toosi University of Technology, Tehran, 2017.
"The EPFL Junctionless FETs model," MOS-AK Workshop, London, 2014.
Between Jun 2009 and February 2010, designing and implementing (SD and HD) broadcast systems in SAMIM-RAYANEH Co., Tehran, Iran.
From April 2010 to November 2011, as a SCADA expert, Tehran Regional Electric Co. (TREC), Tehran, Iran.
"Nano-organic materials in Neural systems," Presentation in nano-organic Course, K.N.Toosi, University of Technology, June 2010.
"Mapping of DSP algorithms on Field Programmable Function Arrays," Presentation in Custom Implementation of DSP Systems Course, University of Tehran, June 2007.
"Analysis and measurement of signal distortion in RF application," Presentation in Analog Integrated Circuits Design Course, University of Tehran, Dec. 2006.
"Sub Millimeter wave detectors, "Presentation in Semiconductor Devices Course, University of Tehran, Dec. 2006.
"Optical transistors and photonic crystals," Presentation in Opto-Electronic Course, University of Tehran, September 2007.
A. Beckers; F. Jazaeri; H. Bohuslavskyi; L. Hutin; S. De Franceschi et al. : Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing. 2018. EUROSOI-ULIS 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, Granada, Spain, March 19–21, 2018.
A. Beckers; F. Jazaeri; A. Ruffino; C. Bruschini; A. Baschirotto et al. : Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing. 2017. Solid-State Device Research Conference (ESSDERC), 2017 47th European, Leuven, Belgium,, 11-14 Sept. 2017. DOI : 10.1109/ESSDERC.2017.8066592.
A. Saeidi; F. Jazaeri; F. Bellando; I. Stolichnov; C. Enz et al. : Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation. 2017. Solid-State Device Research Conference (ESSDERC), 2017 47th European, Leuven, Belgium, 11-14 Sept. 2017. DOI : 10.1109/ESSDERC.2017.8066596.
C.-M. Zhang; F. Jazaeri; A. Pezzotta; C. Bruschini; G. Borghello et al. : Total Ionizing Dose Effects on Analog Performance of 28 nm Bulk MOSFETs. 2017. 47th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, Belgium, September 11-14, 2017. p. 30-33. DOI : 10.1109/ESSDERC.2017.8066584.
M. Coustans; F. Jazaeri; C. Enz; F. Krummenacher; M. Kayal et al. : Variability of Low Frequency Noise and mismatch in CORNER DOPED and standard CMOS technology. 2017. 2017 International Conference on Noise and Fluctuations (ICNF), Vilnius, Lithuania, 20-23 June 2017. p. 1-4. DOI : 10.1109/ICNF.2017.7985953.
C.-M. Zhang; F. Jazaeri; A. Pezzotta; C. Bruschini; G. Borghello et al. : GigaRad Total Ionizing Dose and Post-Irradiation Effects on 28 nm Bulk MOSFETs. 2016. Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD), Strasbourg, France, France, October 29 - November 6, 2016. DOI : 10.1109/NSSMIC.2016.8069869.
A. Pezzotta; C.-M. Zhang; F. Jazaeri; C. Bruschini; G. Borghello et al. : Impact of GigaRad Ionizing Dose on 28nm Bulk MOSFETs for Future HL-LHC. 2016. 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, September 12-15, 2016. p. 146-149. DOI : 10.1109/ESSDERC.2016.7599608.
A. Yesayan; S. Petrosyan; F. Jazaeri; J.-M. Sallese : Effect of interface traps on electrical characteristics of nanowires and nanowire junctionless FETs. 2016. International Conference on Microwave and THz Technologies, Photonics and Wireless Communications, Institute of Radiophysics and Electronics, National Academy of Sciences, Yerevan, Armenia, May 4-6, 2016.
F. Jazaeri; A. Sammak; B. Forouzandeh : Nanoscale Field Effect Diode as a high frequency and ultra lowpower variable gain amplifier in AGC circuits. 2008. 2008 International Conference on Microelectronics - ICM, Sharjah, United Arab Emirates, 14-17 December 2008. p. 317-320. DOI : 10.1109/ICM.2008.5393524.
F. Jazaeri; S. Soleimani-Amiri; B. Ebrahimi; B. Forouzandeh; H.-R. Ahmadi et al. : Pseudo-linear Automatic Gain Control system based on Nanoscale Field Effect Diode and SOI-MOSFET. 2008. 2008 3rd International Design and Test Workshop (IDT), Monastir, Tunisia, 20-22 December 2008. p. 154-158. DOI : 10.1109/IDT.2008.4802487.
F. Jazaeri : Advanced Engineering Mathematics and Methods to Solve PDEs with Matlab ; K.N.Toosi ECE.