Farzan Jazaeri

EPFL STI GR-SCI-IEL
ELB 336 (Bâtiment ELB)
Station 11
1015 Lausanne

Office: ELB 236, ELB 336
EPFL › STI › IEM › GR-SCI-IEL

Expertise

Experimental Solid-State Physics
Quantum Physics
Quantum Computers

Biographie Publications

Farzan Jazaeri received his M.Sc. degree in 2009 from University of Tehran and his Ph.D. in electronic engineering from EPFL in 2015. He has been serving as Research Scientist at EPFL since 2015 and Senior RD Semiconductor Device Engineer in the Swatch Company since 2019.
He is a recipient of the 2018 Electron Devices Society George E. Smith Award, the best talk award from MIXDES 2019 and the best paper awards from ESSDERC2018 and ESSDERC2019, and several other academic awards. He is also awarded an advanced Swiss National Science Foundation grant for two years fellowship in MIT and NASA. Dr. Jazaeri is currently research scientist and project leader in scientific collaborative activities at EPFL.
His research activities on solid-state physics are focused on creation of the cryogenic temperature infrastructure necessary to operate the qubits for quantum computations(MOSQUITO), radiation-induced damages in advanced devices for the future high energy physics experiments at CERN (GigaRadMOST), Pinned Photodiodes for CIS, and modeling and characterization AlGaN-GaN heterostructure in collaboration with IMEC.
Together with Dr. Sallese, he is the lead developer of EPFL HEMT MODEL for GaN HEMTs. He fully developed a new model (EPFL-JL Model) for the so-called nanowire FETs and was invited by Cambridge University Press to write a book on junctionless nanowire FETs, emerging nanoelectronic devices, already published since 2018. He serves as lead editor and reviewer for several scientific journals. He has been an invited keynote speaker at several international conferences and events. He is invited to MIXDES 2019 as a keynote speaker to address quantum bits and quantum computing architecture.
From Jun 2009 to February 2010, he worked on designing and implementing SD/HD broadcast systems with SAMIM-RAYANEH Co., Tehran, Iran.
Between March 2010 and November 2011 he worked as a SCADA expert in Tehran Regional Electric Co. (TREC), Tehran, Iran. From September 2010 to December 2011, he continued his research activities in nano-electronics in Tehran, Iran. In December 2011, he joined to Electron Device Modelling and Technology Lab (EDLab) and pursued his Ph.D. degree at EPFL. In 2015, he received his Ph.D. from Microsystems and Microelectronics department, Integrated Systems Laboratory (STI/IC) at EPFL, Lausanne, Switzerland.

2023

Design space of quantum dot spin qubits

A. Rassekh; M. Shalchian; J.-M. Sallese; F. Jazaeri

Physica B-Condensed Matter. 2023-10-01. DOI : 10.1016/j.physb.2023.415133.

Farzan Jazaeri

Expertise

2023

Design space of quantum dot spin qubits

An improved subthreshold swing expression accounting for back-gate bias in FDSOI FETs

Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement

2022

Back-gate effects on DC performance and carrier transport in 22 nm FDSOI technology down to cryogenic temperatures

Cryogenic RF Characterization and Simple Modeling of a 22 nm FDSOI Technology

Tunneling Current Through a Double Quantum Dots System

High-Temperature HEMT Mode

Accounting for Optical Generation in the Quasi-Neutral Regions of Perovskite Solar Cells

Design Space of Negative Capacitance in FETs

Nonhysteretic Condition in Negative Capacitance Junctionless FETs

2021

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation

Study of Donor-like Surface Trap Emission in GaN HEMTs

Charge-based modeling of ultra narrow junctionless cylindrical nanowire FETs

Generalized Boltzmann relations in semiconductors including band tails

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps

2020

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Transcapacitances in EPFL HEMT Model

Cryo-CMOS Compact Modeling

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Modeling of Short-Channel Effects in GaN HEMTs

Inflection Phenomenon in Cryogenic MOSFET Behavior

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Molecular Engineering of Simple Metal-Free Organic Dyes Derived from Triphenylamine for Dye-Sensitized Solar Cell Applications

2019

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Charge-Based EPFL HEMT Model

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

CJM: A Compact Model for Double-Gate Junction FETs

Cryogenic MOSFET Threshold Voltage Model

Ultrathin Junctionless Nanowire FET Model, Including 2-D Quantum Confinements

Compact Modeling of Charge Transfer in Pinned Photodiodes for CMOS Image Sensors

2018

Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Negative capacitance tunnel F£Ts: Experimental demonstration of outstanding simultaneous boosting of on-current, transconductance, overdrive, and swing

28-nm Bulk and FDSOI Cryogenic MOSFET (Invited Paper)

Mobility Degradation of 28-nm Bulk MOSFETs Irradiated to Ultrahigh Total Ionizing Doses

Bias Dependence of Total Ionizing Dose Effects on 28-nm Bulk MOSFETs

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs-Part II: Total Charges and Transcapacitances

Charge-Based Model for Ultrathin Junctionless DG FETs, Including Quantum Confinement

Charge-based Model for Junction FETs

Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

Characterization and Modeling of 28 nm Bulk CMOS Technology down to Cryogenic Temperatures (4.2 K)

Cryogenic MOS Transistor Model

Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

A Design-oriented Charge-based Simplified Model for FDSOI MOSFETs

Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances

Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

2017

Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing

Carrier Mobility Extraction in FETs

Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation

Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing

Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

Total Ionizing Dose Effects on Analog Performance of 28 nm Bulk MOSFETs

Variability of Low Frequency Noise and mismatch in CORNER DOPED and standard CMOS technology

2016

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

Effect of interface traps on electrical characteristics of nanowires and nanowire junctionless FETs

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

2015

Modeling Junctionless Metal-Oxide-Semiconductor Field-Effect Transistor

FOSS EKV 2.6 parameter extractor