Creating Validated simulation infrastructure for performance estimation of RISC-V architectures.
Enabling Full-System simulation and emulation capabilities with Linux and Zephyr RTOS
FPGA based prototyping of Heterogenous Compute Systems involving accelerators and multi-core systems.
Creating RISC-V debugging infrastructure for high-end FPGAs with HBMs.
Memory backend simulators to study  different technologies and their impact on ML workloads.
Charactersation of Chip-level Interconnect protocol on FPGA.
Baremetal Firmware development (bootloaders, Hardware Performance Counters) for emulated and simulated systems.