Mirjana Stojilovic

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PhD (School of El. Engineering, Belgrade, 2013)

mirjana.stojilovic@epfl.ch +41 21 69 35298

EPFL IC IINFCOM PARSA
INJ 235 (Bâtiment INJ)
Station 14
CH-1015 Lausanne

Site web: http://sin.epfl.ch
Unité: SIN-ENS

Site web: http://ssc.epfl.ch
Unité: SSC-ENS

Données administratives

Publications

Enseignement & Phd

Enseignement

  • Computer Science,
  • Communication Systems

Programmes doctoraux

Doctorants

Cours

Computer architecture

Le cours introduit les étudiants aux concepts de base de l'architecture des ordinateurs et en particulier au choix du répertoire d'instructions et à la hiérarchie mémoire des ordinateurs contemporains. goto


Information, calcul, communication

D'une part, le cours aborde: (1) la notion d'algorithme et de représentation de l'information, (2) l'échantillonnage d'un signal et la compression de données et (3) des aspects liés aux systèmes: ordinateur, mémoire, etc. D'autre part, le cours donne une ... goto


Information, calcul, communication

D'une part, le cours aborde: (1) la notion d'algorithme et de représentation de l'information, (2) l'échantillonnage d'un signal et la compression de données et (3) des aspects liés aux systèmes: ordinateur, mémoire, etc. D'autre part, le cours donne une ... goto


Information, calcul, communication

D'une part, le cours aborde: (1) la notion d'algorithme et de représentation de l'information, (2) l'échantillonnage d'un signal et la compression de données et (3) des aspects liés aux systèmes: ordinateur, mémoire, etc. D'autre part, le cours donne une ... goto


Projet programmation système

L'objectif de ce cours à projet est de donner aux étudiants une expérience de la pratique de la programmation système : écriture, correction, amélioration et analyse critique de leur code. goto


Recherche

Acceleration of FPGA compilation

As transistor scaling is slowing down, other opportunities for ensuring continuous performance increase have to be discovered and explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud. This makes them available to everyone in need of the immense computing power and data throughput they can offer.

Yet, there are stil issues that stand in the way of massive popularization of FPGAs: These days, the time to compile an industrial-scale circuit is in the order of hours or even days, depending on the size of the circuit. Since every design is modified many times before it is ready for deployment, these long compilation
times not only seriously affect the time-to-market but also further alienate both existing and future FPGA designers from FPGAs.

In our research, we attack the issue of time-consuming FPGA compilation through various forms of hardware/software parallelism.

HW acceleration of EM modelling and simulation

Predicting and understanding electromagnetic (EM) behavior of circuits and systems is important for many engineering disciplines. Widely used EM modelling and simulation algorithms require a lot of computing resources (both memory and processing power), and yet often take prohibitively long times to complete the analysis of a realistically large models.

In our research, we explore the acceleration opportunities offered by heterogeneous hardware platforms, for various EM modelling approaches and target scenarios.