Semester and diploma projects
Interconnect pipelining in Stratix-10 FPGAs
Type of work: Semester project
Contact:
Mirjana Stojilovic
Intel's Stratix-10 FPGA is a new-wave of FPGA architectures that feature pipeline registers in the routing, to enable much higher circuit speed.
In this project, your task will be to learn Stratix-10 FPGA architecture and the new approaches that are taken to routing an FPGA design on such an architecture. You will implement a test design in VHDL (or Verilog, or Chisel), and analyze the timing achieved by the tool.
Additional reading:
href="http://www.isfpga.org/fpga2016/index_files/Slides/5_2.pdf">
href="https://aws.amazon.com/ec2/instance-types/f1/">
Introduction to Amazon EC2 F1 Instances
Type of work: Semester project
Contact:
Mirjana Stojilovic
Amazon EC2 F1 is a compute instance with field programmable gate arrays (FPGAs) that one can program to create custom hardware accelerators for an application. In this project, your task will be to get familiar with the features of and the tools for configuring Amazon's FPGA-accelerated cloud instances, and to port one of our side-channel attack FPGA-designs to the Amazon cloud.
Additional reading:
href="https://github.com/aws/aws-fpga">
href="https://aws.amazon.com/ec2/instance-types/f1/">
Power Analysis Side-Channel Attack on the AES encryption algorithm in a realistic working environment
Type of work: Semester project
Contact:
Mirjana Stojilovic
It is known that an unprotected AES encryption core can be attacked successfully using correlation power analysis, when that core is (almost) the only system running on an FPGA. Can we say the same when there are multiple AES cores encrypting different data with different keys? Can we say the same when next to the AES encryption cores we have other digital logic implementing unrelated algorithms?
The goal of this project would be to learn what is side-channel analysis, learn how to do it in practice, and measure the number of power traces required to successfully attack an unprotected AES encryption core (break the key) in presence on other active digital logic on the same FPGA.
FPGA On-Chip Digital Voltage Sensor Design
Type of work: Semester project
Contact:
Mirjana Stojilovic
In this project, your task will be to improve the basic design of a delay-line-based digital sensor on FPGA, with the goal of increasing its maximum operating frequency and achieving as high as possible measurement rate.
Implementation of a Constraint-driven Parallel Algorithm for Graph Coloring
Type of work: Semester or diploma project
Contact:
Mirjana Stojilovic
In this project, your task will be to write a parallel algorithm for graph coloring, implement it in C , and test (and profile the execution) using Cilk, Open MP, and Galois parallel programming environments.
FPGA implementation of electromagnetic time-reversal algorithm
Type of work: Semester project
Contact:
Mirjana Stojilovic
The electromagnetic (EM) time-reversal method is based on the simultaneous, synchronized recording of the electric and/or the magnetic field waveforms at several EM-field sensors. The recorded waveforms are numerically time-reversed and back-propagated into the space. The maximum constructive interference of these back-propagated signals occurs where the source of the EM field lies. Hence, this method can be used to localize many different sources
of EM field.
(read more here)
In this project, your task will be to design an FPGA circuit that can process and analyze the recorded waveform, and output the location of the EM disturbance.
