Courses

Research

Acceleration of FPGA compilation

As transistor scaling is slowing down, other opportunities for ensuring continuous performance increase have to be discovered and explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud. This makes them available to everyone in need of the immense computing power and data throughput they can offer. Yet, there are stil issues that stand in the way of massive popularization of FPGAs: These days, the time to compile an industrial-scale circuit is in the order of hours or even days, depending on the size of the circuit. Since every design is modified many times before it is ready for deployment, these long compilation times not only seriously affect the time-to-market but also further alienate both existing and future FPGA designers from FPGAs. In our research, we attack the issue of time-consuming FPGA compilation through various forms of hardware/software parallelism.

HW acceleration of EM modelling and simulation

Predicting and understanding electromagnetic (EM) behavior of circuits and systems is important for many engineering disciplines. Widely used EM modelling and simulation algorithms require a lot of computing resources (both memory and processing power), and yet often take prohibitively long times to complete the analysis of a realistically large models. In our research, we explore the acceleration opportunities offered by heterogeneous hardware platforms, for various EM modelling approaches and target scenarios.