Paolo Ienne

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Full Professor

paolo.ienne@epfl.ch +41 21 693 26 25

Secretariat
Chantal Schneeberger Building INF136 Station 14 CH-1015 Lausanne Tel. + 41 21 693 26 41 chantal.schneeberger@epfl.ch

EPFL IC IINFCOM LAP
INF 137 (Bâtiment INF)
Station 14
CH-1015 Lausanne

EPFL IC SIN-GE
INF 137 (Bâtiment INF)
Station 14
CH-1015 Lausanne

Web site: https://ssc.epfl.ch
Unit: SSC-ENS

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Administrative data

Fields of expertise

Computer and Processor Architecture, FPGAs and Reconfigurable Computing, Electronic Design Automation, Computer Arithmetic.

Publications

Other publications

Hadi Parandeh-Afshar, Hind Benbihi, David Novo Bruna, and Paolo Ienne
In Proceedings of the 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., February 2012. Best Paper Award.
Rethinking FPGAs: Elude the flexibility excess of LUTs with And-Inverter Cones.
Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne
In Proceedings of the 19th International Conference on Field-Programmable Logic and Applications, pages 242-49, Prague, August 2009. Best Paper Award
Exploiting fast carry-chains of FPGAs for designing compressor trees
Ajay K. Verma, Philip Brisk, and Paolo Ienne
In Proceedings of the International Conference on Computer Aided Design, San Jose, Calif., November 2009
Iterative Layering: Optimizing arithmetic circuits by structuring the information flow
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, and Paolo Ienne
In High Performance Embedded Architectures and Compilers, volume 5952 of Lecture Notes in Computer Science, pages 126-40. Springer, 2010. Best Paper Award Nominee
Virtual Ways: Efficient coherence for architecturally visible storage in automatic instruction set extensions
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Chrysostomos Nicopoulos, Seyed Hosein Attarzadeh Niaki, Frank K. Gurkaynak, Yusuf Leblebici, and Paolo Ienne
ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2(2):13:1-13:36, June 2009
Field programmable compressor trees: Acceleration of multi-input addition on FPGAs
Ajay K. Verma, Philip Brisk, and Paolo Ienne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-29(3):341-54, March 2010
Fast, nearly-optimal ISE identification with I/O serialisation through maximal clique enumeration
Ajay K. Verma, Philip Brisk, and Paolo Ienne
In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pages 125-34, Salzburg, September 2007. Best Paper Award
Rethinking custom ISE identification: A new processor agnostic method
Laura Pozzi, Kubilay Atasu, and Paolo Ienne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1209-29, July 2006
Exact and approximate algorithms for the extension of embedded processor instruction sets
Kubilay Atasu, Laura Pozzi, and Paolo Ienne
In Proceedings of the 40th Design Automation Conference, Anaheim, Calif., June 2003. Best Paper Award
Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints

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