Giovanni Ansaloni
+41 21 693 88 09
Office:
ELG 137
EPFL › STI › IEM › ESL
Website: https://esl.epfl.ch
Crossing the Layers and Dotting the Details: Systematic Exploration of Near-Memory Computing
2026. ISQED'26 The 27th International Symposium on Quality Electronic Design, San Francisco, California, USA, 2026-04-08 - 2026-04-10.Towards Accurate RISC-V Full System Simulation via Component-level Calibration
ACM Transactions on Embedded Computing Systems. 2025. DOI : 10.1145/3737876.A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces
2025. 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025-05-25 - 2025-05-28. p. 1 - 5. DOI : 10.1109/iscas56072.2025.11044062.Personalization on a Budget: Minimally-Labeled Continual Learning for Resource-Efficient Seizure Detection
2025Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications
2025. The 26th International Symposium on Quality Electronic Design, San Francisco, CA, US, 2025-04-23 - 2025-04-25.LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles
IEEE Transactions on Emerging Topics in Computing. 2025. DOI : 10.1109/TETC.2025.3546128.HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge
2025. Computer Frontiers Workshop on Open-Source Hardware, Cagliari, Sardinia, Italy, 2025-05-28 - 2025-05-30. DOI : 10.1145/3706594.3726967.Structured pruning for efficient systolic array accelerated cascade Speech-to-Text Translation
2025. 26th Interspeech Conference 2025, Rotterdam, The Netherlands, 2025-08-17 - 2025-08-21.Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
IEEE Embedded Systems Letters. 2025. DOI : 10.1109/les.2025.3631154.SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation
2025. International Conference on Hardware/Software Codesign and System Synthesis, Taipei, Taiwan, 2025-09-29 - 2025-10-01. DOI : 10.1145/3762641.Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
35th Great Lakes Symposium on VLSI, New Orleans, LA, USA, 2025-06-30 - 2025-07-02.X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
2025Resource-Efficient Continual Learning for Personalized Online Seizure Detection
2024. 46th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Orlando, Florida, USA, 2024-07-15 - 2024-07-19. p. 1 - 7. DOI : 10.1109/EMBC53108.2024.10781699.Bank on Compute-near-Memory: Design Space Exploration of Processing-near-Bank Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024. DOI : 10.1109/TCAD.2024.3442989.An Open-Source and Configurable RISC-V CPU/GPU Accelerated Processing Unit for Ultra-Low-Power Wearable Devices
SMARTHEP Edge Machine Learning School, CERN, Meyrin, Switzerland, 2024-09-23 - 2024-09-27.Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware
2024. 29 ACM/IEEE International Symposium on Low Power Electronics and Design, Newport Beach, United States, 2024-08-05 - 2024-08-07. DOI : 10.1145/3665314.3680474.Which Coupled is Best Coupled? An Exploration of AIMC Tile Interfaces and Load Balancing for CNNs
IEEE Transactions on Parallel and Distributed Systems. 2024. DOI : 10.1109/TPDS.2024.3437657.SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
ACM Journal on Emerging Technologies in Computing Systems. 2024. DOI : 10.48550/arXiv.2402.12834.An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2024. DOI : 10.1109/TVLSI.2024.3375793.Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
2024. 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024), Munich, Germany, January 18, 2024. DOI : 10.4230/OASIcs.PARMA-DITAM.2024.3.FVLLMONTI: The 3D Neural Network Compute Cube (N2C2) Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation
2024. 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024-03-25 - 2024-03-27. p. 5112 - 5116.REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal
2023. 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Dubai, United Arab Emirates, October 16-18, 2023. DOI : 10.1109/VLSI-SoC57769.2023.10321912.Event-based sampled ECG morphology reconstruction through self-similarity
Computer Methods And Programs In Biomedicine. 2023. DOI : 10.1016/j.cmpb.2023.107712.Overflow-free Compute Memories for Edge AI Acceleration
Acm Transactions On Embedded Computing Systems. 2023. DOI : 10.1145/3609387.An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing
2023. CF23-OSHW: Computing Frontiers Workshop on Open-Source Hardware, Bologna, Italy, May 9-11, 2023. DOI : 10.1145/3587135.3591437.TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers
2023. ASP-DAC 2023, Tokyo, Japan, January 16-19, 2023. DOI : 10.1145/3566097.3567867.Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference
IEEE Transactions on Emerging Topics in Computing. 2023. DOI : 10.1109/TETC.2023.3237914.System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms
2023. 28th Asia and South Pacific Design Automation Conference (ASPDAC '23), Tokyo, Japan, January 16-19, 2023. DOI : 10.1145/3566097.3567952.Overflow-free compute memories for edge AI acceleration
2023. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2023), Hamburg, Germany, September 17-22, 2023. DOI : 10.1145/3607888.3609284.Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures
2023. Design, Automation and Test in Europe Conference and Exhibition (DATE), Antwerp, BELGIUM, Apr 17-19, 2023. DOI : 10.23919/DATE56975.2023.10136923.ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning
IEEE Transactions on Computers (TC). 2022. DOI : 10.1109/TC.2022.3230285.Using Algorithmic Transformations and Sensitivity Analysis to Unleash Approximations in CNNs at the Edge
MDPI Micromachines - Special Issue "Hardware-Friendly Machine Learning and Its Applications". 2022. DOI : 10.3390/mi13071143.Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge
2022. Great Lakes Symposium on VLSI 2022 (GLSVLSI ’22), Irvine, California, USA, June 6-8, 2022. DOI : 10.1145/3526241.3530351.A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis
Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems. 2022. DOI : 10.1109/TCAD.2021.3075651.Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures
2022. 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), Santiago de Chile, Chile, March 1-4, 2022. p. 1 - 4. DOI : 10.1109/LASCAS53948.2022.9893905.Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022. DOI : 10.1109/TCAD.2022.3168257.Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays
2022. 32nd Great Lakes Symposium on VLSI (GLSVLSI 2022), Irvine, California, USA, June 6-8, 2022. DOI : 10.1145/3526241.3530309.An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs
2022. IEEE International Conference on Omni-Layer Intelligent Systems (COINS), Barcelona, Spain, August 1-3, 2022. DOI : 10.1109/COINS54846.2022.9854986.A hardware/software co-design vision for deep learning at the edge
IEEE Micro. 2022. DOI : 10.1109/MM.2022.3195617.DB4HLS: A Database of High-Level Synthesis Design Space Explorations
Ieee Embedded Systems Letters. 2021. DOI : 10.1109/LES.2021.3066882.A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs
2021. IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida, USA (Virtual), July 7-9, 2021. p. 164 - 169. DOI : 10.1109/ISVLSI51109.2021.00039.Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing
2021. DATE 2021 Design, Automation and Test in Europe Conference, Virtual Conference and Exhibition, February 1-5, 2021. p. 1881 - 1886. DOI : 10.23919/DATE51398.2021.9474233.Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding
2021. 58th Design Automation Conference (DAC), San Francisco, California, USA, December 5-9, 2021. p. 805 - 810. DOI : 10.1109/DAC18074.2021.9586245.i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing
IEEE Embedded Systems Letters (ESL). 2019. DOI : 10.1109/LES.2018.2849267.Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors
2019. Design, Automation & Test in Europe Conference (DATE), Florence, Italy, 25-29 March 2019. p. 948 - 951. DOI : 10.23919/DATE.2019.8714858.Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications
2018. The International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 27-30, 2018. DOI : 10.1109/ISCAS.2018.8351595.An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery
ACM Transactions on Embedded Computing Systems. 2017. DOI : 10.1145/3126565.An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery
2017. CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis, Seoul, South Korea, October 15-20, 2017.Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes
2016. CODES-ISSS 2016, Pittsburgh, USA, 01-06.10.2016. DOI : 10.1145/2968456.2968464.A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis
2016. Biomedical Circuits and Systems (BioCAS), Shanghai, China, October 17-19, 2016. p. 416 - 419. DOI : 10.1109/BioCAS.2016.7833820.Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis
IET Computers & Digital Techniques. 2016. DOI : 10.1049/iet-cdt.2015.0194.Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices
2015. IEEE Annual Symposium on VLSI 2015 (ISVLSI 2015), Montpellier, France, July 8-10, 2015. p. 173 - 180. DOI : 10.1109/ISVLSI.2015.46.Method for detecting abnormalities in an electrocardiogram
US9468386 ; US2015257668 . 2015.Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes
Sensors. 2014. DOI : 10.3390/s141222532.Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes
2014. IEEE/ACM 2014 Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, March 24-28, 2014. p. 50 - 55. DOI : 10.7873/DATE.2014.181.Ultra-Low Power Design of Wearable Cardiac Monitoring Systems
2014. IEEE/ACM 2014 Design Automation Conference (DAC), San Francisco, CA, USA, June 1-5, 2014. p. 140 - 145. DOI : 10.1145/2593069.2596691.Hardware-Software Inexactness in Noise-aware Design of Low-Power Body Sensor Nodes
2014. Designing with Uncertainty - Opportunities & Challenges, York, United Kingdom, March 17-19 , 2014.Ultra-Low Power Design of Wearable Cardiac Monitoring Systems
2014. 51st ACM/EDAC/IEEE Design Automation Conference (DAC). DOI : 10.1145/2593069.2596691.Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach
Computers in Cardiology. 2014.A Methodology for Embedded Classification of Heartbeats Using Random Projections
2013. DATE2013, Grenoble, France, March 18-22, 2013. p. 899 - 904. DOI : 10.7873/DATE.2013.189.Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms
2013. The Design, Automation and Test in Europe (DATE), 2013, Grenoble, France. p. 396 - 399. DOI : 10.7873/DATE.2013.090.Embedded Real-Time ECG Delineation Methods: a Comparative Evaluation
2012. IEEE 12th International Conference on BioInformatics and BioEngineering (BIBE 2012), IEEE Press, Larnaca, Cyprus, November 11-13, 2012. p. 99 - 104. DOI : 10.1109/BIBE.2012.6399715.Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2012. DOI : 10.1109/Tcad.2012.2209886.Architectural Exploration and Scheduling Methods for Coarse Grained Reconfigurable Arrays
Università della Svizzera italiana (Lugano, Switzerland), 2011.Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.
2009. Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09, Nice, France, 20-24 April 2009. p. 542 - 547. DOI : 10.1109/DATE.2009.5090723.Compiling custom instructions onto expression-grained reconfigurable architectures
2008. international conference on Compilers, architectures and synthesis for embedded systems (CASES), Atlanta, Georgia, USA, October 19-24, 2008. p. 51 - 60. DOI : 10.1145/1450095.1450106.Teaching & PhD
PhD Students
Yuxuan Wang, Grégoire Axel Eggermann, Riselda Kodra, Patrik Kukic
Courses
Lab on app development for tablets and smartphones
EE-490(g)
Focusing on the Android ecosystem, this course teaches techniques for the development of distributed mobile applications, operating on multiple heterogeneous devices (tablets / smartwatches), sensing the environment, and interfacing with the cloud.