David Atienza Alonso
Nationalité: Spanish and Swiss
+41 21 693 11 31
Office: ELG 130
EPFL › VPA › VPA-AVP-CP › AVP-CP › AVP-CP-GE
EPFL STI IEM ESL
ELG 130 (Bâtiment ELG)
Station 11
1015 Lausanne
+41 21 693 11 32
+41 21 693 11 31
Office: ELG 130
EPFL › STI › IEM › ESL
Site web: https://esl.epfl.ch
+41 21 693 11 31
Office: ELG 130
EPFL › VPA › VPA-AVP-DLE › AVP-DLE-EDOC › EDEE-ENS
Expertise
Expertise
Publications représentatives
Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers
Ali Pahlevan, Xiaoyu Qu, Marina Zapater, David Atienza
Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37, No. 8, pp. 1667-1680, IEEE Press, August 2018. in
HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis
Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
Published in IEEE Transactions on Circuits and Systems: Part I (TCAS-I), Vol. 64, Issue: 9, pp. 2448-2461, IEEE Press, September 2017. in
Big-Data Streaming Applications Scheduling Based on Staged Multi-Armed Bandits
Karim Kanoun, Cem Tekin, David Atienza, Mihaela van der Schaar
Published in IEEE Transactions on Computers, Vol. 65, Issue: 12, pp. 3591-3605, IEEE Computer Society, December 2016. in
3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs
Arvind Sridhar, Alessandro Vincenzi, David Atienza, Thomas Brunschwiler
Published in IEEE Transactions on Computers, Vol. 63, Issue: 10, pp. 2576-2589, IEEE Computer Society, October 2014. in
Compressed Sensing for Real-Time Energy-Efficient ECG Compression on Wireless Body Sensor Nodes
Hossein Mamaghanian, Nadia Khaled, David Atienza, Pierre Vandergheynst
Published in IEEE Transactions on Biomedical Engineering, Vol. 58, No. 12, pp. 120-129, IEEE Press, September 2011. in
Development and Evaluation of Multi-Lead Wavelet-Based ECG Delineation Algorithms for Embedded Wireless Sensor Nodes
Francisco Rincon, Joaquin Recas, Nadia Khaled, David Atienza
Published in IEEE Transactions on Information Technology in BioMedicine, Vol. 16, Nr. 11, pp. 1-9, IEEE Press, November 2011. in
Doctorant·es actuel·les
Lara Orlandic, Simone Machetti, Hossein Taji, Yuxuan Wang, Rafael Medina Morillas, Pengbo Yu, Qunyou Liu, Hojjat Karami, Karan Pathak, Stasa Kostic, Anna Burdina, Clément Renaud Jean Choné, Grégoire Axel Eggermann, Dimitrios Samakovlis, Christodoulos Kechris, Mingfei Yu, Stefano Albini, Amirhossein Shahbazinia, Riselda Kodra, Juan Sapriza, Rubén Rodríguez Álvarez, Kai Zhu, Golnoosh Abdollahinejad, Dimitra Tatli, Tommaso Terzano, Wensi Zhang
A dirigé les thèses EPFL de
Mohamed Mostafa Sabry Aly, Ahmed Yasir Dogan, Arvind Sridhar, Hossein Mamaghanian, Shivani Raghav, Ivan Beretta, Karim Kanoun, Ruben Braojos Lopez, Loris Gérard Duch, Soumya Subhra Basu, Ali Pahlevan, Grégoire Surrel, Fabio Isidoro Tiberio Dell'Agnola, Dionisije Sopic, Arman Iranfar, Elisabetta De Giovanni, Yasir Mahmood Qureshi, Halima Najibi, William Andrew Simon, Farnaz Forooghifar, Benoît Walter Denkinger, Una Pale, Renato Zanetti, Flavio Ponzina, Saleh Baghersalimi, Marco Antonio Rios, Joshua Alexander Harrison Klein, Silvio Zanoli, Giulio Masinelli, Darong Huang, Alireza Amirshahi
Jeremy Hugues-Felix Constantin
Cours
Design and Optimization of Internet-of-Things Systems
This course provides a complete overview of the most relevant subfields related to Internet of Things (IoT) systems, it presents the perspectives and the underlying technologies, with a particular focus on edge AI architectures and software (AI and TinyML algorithms), communication and Cloud systems
Lab on hardware-software digital systems codesign
EE-390(a)
Ce cours explore les techniques de concevoir conjointement la partie matérielle et logicielle pour développer des systèmes embarqués multicœurs hétérogènes exécutant Linux sur FPGA. Le cours explore les outils de synthèse de haut niveau (HLS) pour concevoir des accélérateurs matériels qui réduisent
Systèmes embarqués microprogrammés
L'étudiant comprendra les architectures des systèmes embarqués microprogrammés, les architectures des microprocesseurs, hiérarchie de mémoire et les différents périphériques de Entrée/Sortie (E/S) inclus, utilisant comme étude de cas la plate-forme portable Nintendo DS.