Giovanni Ansaloni

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giovanni.ansaloni@epfl.ch +41 21 693 88 09

EPFL STI IEL ESL
ELG 137 (Bâtiment ELG)
Station 11
CH-1015 Lausanne

+41 21 693 88 09
Local: ELG 137
EPFL > STI > IEM > ESL

Web site: Site web: https://esl.epfl.ch

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Publications

Publications Infoscience

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.

G. Ansaloni; P. Bonzini; L. Pozzi

2008. Symposium on Application Specific Processors, 2008. (SASP08), Anaheim, California, USA, 8-9 June 2008. p. 26-33. DOI : 10.1109/SASP.2008.4570782.

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Compiling custom instructions onto expression-grained reconfigurable architectures

P. Bonzini; G. Ansaloni; L. Pozzi

2008. international conference on Compilers, architectures and synthesis for embedded systems (CASES), Atlanta, Georgia, USA, October 19-24, 2008. p. 51-60. DOI : 10.1145/1450095.1450106.

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Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.

G. Ansaloni; P. Bonzini; L. Pozzi

2009. Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09, Nice, France, 20-24 April 2009. p. 542-547. DOI : 10.1109/DATE.2009.5090723.

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Architectural Exploration and Scheduling Methods for Coarse Grained Reconfigurable Arrays

G. Ansaloni

Università della Svizzera italiana (Lugano, Switzerland), 2011.

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Slack-aware scheduling on Coarse Grained Reconfigurable Arrays

G. Ansaloni; K. Tanimura; L. Pozzi; N. Dutt

2011. Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2011. p. 1-4. DOI : 10.1109/DATE.2011.5763323.

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EGRA: A Coarse Grained Reconfigurable Architectural Template

G. Ansaloni; P. Bonzini; L. Pozzi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2011. DOI : 10.1109/TVLSI.2010.2044667.

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Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

G. Ansaloni; K. Tanimura; L. Pozzi; N. Dutt

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2012. DOI : 10.1109/Tcad.2012.2209886.

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IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring

M. Milis; K. Michaelides; A. Kounoudes; G. Ansaloni; D. Atienza Alonso et al.

2012. IEEE 12th International Conference on BioInformatics and BioEngineering (BIBE 2012), Larnaca, Cyprus, November 11-13, 2012. p. 105-109. DOI : 10.1109/BIBE.2012.6399716.

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Embedded Real-Time ECG Delineation Methods: a Comparative Evaluation

R. Braojos Lopez; G. Ansaloni; D. Atienza Alonso; R. Vallejos; F. Javier

2012. IEEE 12th International Conference on BioInformatics and BioEngineering (BIBE 2012), IEEE Press, Larnaca, Cyprus, November 11-13, 2012. p. 99-104. DOI : 10.1109/BIBE.2012.6399715.

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A Methodology for Embedded Classification of Heartbeats Using Random Projections

R. Braojos Lopez; G. Ansaloni; D. Atienza Alonso

2013. DATE2013, Grenoble, France, March 18-22, 2013. p. 899-904. DOI : 10.7873/DATE.2013.189.

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Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

A. Y. Dogan; R. Braojos Lopez; J. H.-F. Constantin; G. Ansaloni; A. P. Burg et al.

2013. The Design, Automation and Test in Europe (DATE), 2013, Grenoble, France. p. 396-399. DOI : 10.7873/DATE.2013.090.

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Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes

R. Braojos; I. Beretta; G. Ansaloni; D. Atienza Alonso

Sensors. 2014. DOI : 10.3390/s141222532.

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Ultra-Low Power Design of Wearable Cardiac Monitoring Systems

R. Braojos; H. Mamaghanian; A. Dias Junior; G. Ansaloni; D. Atienza et al.

2014. 51st ACM/EDAC/IEEE Design Automation Conference (DAC). DOI : 10.1145/2593069.2596691.

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Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach

J. Milosevic; A. Dittrich; A. Ferrante; M. Malek; D. C. Rojas Quirós et al.

Computers in Cardiology. 2014.

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Hardware-Software Inexactness in Noise-aware Design of Low-Power Body Sensor Nodes

H. Mamaghanian; G. Ansaloni; M. M. S. Aly; D. Atienza Alonso; P. Vandergheynst

2014. Designing with Uncertainty - Opportunities & Challenges, York, United Kingdom, March 17-19 , 2014.

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Power-Efficient Joint Compressed Sensing of Multi-Lead ECG Signals

H. Mamaghanian; G. Ansaloni; D. Atienza Alonso; P. Vandergheynst

2014. 39th International Conference on Acoustics, Speech and Signal Processing (ICASSP 2014), Florence, Italy, May 5-9 2014. p. 4409-4412. DOI : 10.1109/ICASSP.2014.6854435.

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Ultra-Low Power Design of Wearable Cardiac Monitoring Systems

R. Braojos Lopez; H. Mamaghanian; R. Vallejos; F. Javier; A. Dias Junior et al.

2014. IEEE/ACM 2014 Design Automation Conference (DAC), San Francisco, CA, USA, June 1-5, 2014. p. 140-145. DOI : 10.1145/2593069.2596691.

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Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

R. Braojos Lopez; I. Beretta; G. Ansaloni; D. Atienza Alonso

2014. IEEE/ACM 2014 Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, March 24-28, 2014. p. 50-55. DOI : 10.7873/DATE.2014.181.

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Method for detecting abnormalities in an electrocardiogram

R. Braojos Lopez; G. Ansaloni; D. Atienza Alonso; F. J. Rincon Vallejos; S. Murali

US9468386 ; US2015257668 . 2015.

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Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices

S. S. Basu; P. Garcia del Valle; G. Ansaloni; G. Karakonstantis; D. Atienza Alonso

2015. IEEE Annual Symposium on VLSI 2015 (ISVLSI 2015), Montpellier, France, July 8-10, 2015. p. 173-180. DOI : 10.1109/ISVLSI.2015.46.

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Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes

R. Braojos Lopez; T. F. Wu; G. Ansaloni; M. M. Sabry Aly; D. Atienza et al.

2016. CODES-ISSS 2016, Pittsburgh, USA, 01-06.10.2016. DOI : 10.1145/2968456.2968464.

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A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

L. G. Duch; S. S. Basu; R. Braojos Lopez; G. Ansaloni; L. Pozzi et al.

2016. Biomedical Circuits and Systems (BioCAS), Shanghai, China, October 17-19, 2016. p. 416-419. DOI : 10.1109/BioCAS.2016.7833820.

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Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

S. S. Basu; P. Garcia del Valle; G. Karakonstantis; G. Ansaloni; L. Pozzi et al.

IET Computers & Digital Techniques. 2016. DOI : 10.1049/iet-cdt.2015.0194.

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An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

S. Basu; L. Duch; R. Braojos; G. Ansaloni; L. Pozzi et al.

ACM Transactions on Embedded Computing Systems. 2017. DOI : 10.1145/3126565.

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An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

S. S. Basu; L. G. Duch; R. Braojos Lopez; G. Ansaloni; L. Pozzi et al.

2017. CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis, Seoul, South Korea, October 15-20, 2017.

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HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

L. G. Duch; S. S. Basu; R. Braojos Lopez; G. Ansaloni; L. Pozzi et al.

IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. DOI : 10.1109/Tcsi.2017.2701499.

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A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

R. Braojos Lopez; D. Bortolotti; A. Bartolini; G. Ansaloni; L. Benini et al.

IEEE Transactions on Computers. 2017. DOI : 10.1109/TC.2016.2610426.

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Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications

S. S. Basu; L. G. Duch; M. Peon Quiros; G. Ansaloni; L. Pozzi et al.

2018. The International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 27-30, 2018. DOI : 10.1109/ISCAS.2018.8351595.

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Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors

L. Ferretti; G. Ansaloni; L. Pozzi; A. Aminifar; D. Atienza Alonso et al.

2019. Design, Automation & Test in Europe Conference (DATE), Florence, Italy, 25-29 March 2019. DOI : 10.23919/DATE.2019.8714858.

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i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

L. G. Duch; S. S. Basu; M. Peon Quiros; G. Ansaloni; L. Pozzi et al.

IEEE Embedded Systems Letters (ESL). 2019. DOI : 10.1109/LES.2018.2849267.

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Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

C. Maneux; C. Mukherjee; M. Deng; M. Dubourg; L. Reveil et al.

2021. 67th Annual IEEE International Electron Devices Meeting (IEDM 2021), San Francisco, California, USA, December 11-15, 2021.

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Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding

W. A. Simon; V. Rey; A. S. J. Levisse; G. Ansaloni; M. Zapater Sancho et al.

2021. 58th Design Automation Conference (DAC), San Francisco, California, USA, December 5-9, 2021. p. 805-810. DOI : 10.1109/DAC18074.2021.9586245.

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Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

M. A. Rios; F. Ponzina; G. Ansaloni; A. S. J. Levisse; D. Atienza Alonso

2021-02-01. DATE 2021 Design, Automation and Test in Europe Conference, Virtual Conference and Exhibition, February 1-5, 2021. p. 1881-1886. DOI : 10.23919/DATE51398.2021.9474233.

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A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs

F. Ponzina; M. A. Rios; G. Ansaloni; A. S. J. Levisse; D. Atienza Alonso

2021-07-07. IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida, USA (Virtual), July 7-9, 2021. p. 164-169. DOI : 10.1109/ISVLSI51109.2021.00039.

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DB4HLS: A Database of High-Level Synthesis Design Space Explorations

L. Ferretti; J. Kwon; G. Ansaloni; G. Di Guglielmo; L. Carloni et al.

Ieee Embedded Systems Letters. 2021-12-01. DOI : 10.1109/LES.2021.3066882.

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An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

F. Ponzina; M. Peon Quiros; G. Ansaloni; D. Atienza Alonso

2022. IEEE International Conference on Omni-Layer Intelligent Systems (COINS), Barcelona, Spain, August 1-3, 2022.

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Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

H. Najibi; A. S. J. Levisse; G. Ansaloni; M. Zapater Sancho; Miroslav Vasic et al.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)). 2022. DOI : 10.1109/TCAD.2022.3168257.

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Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

H. Najibi; A. S. J. Levisse; G. Ansaloni; M. Zapater Sancho; D. Atienza Alonso

2022. 32nd Great Lakes Symposium on VLSI (GLSVLSI 2022), Irvine, California, USA, June 6-8, 2022. DOI : 10.1145/3526241.3530309.

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INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

L. Ferretti; G. Ansaloni; R. Marquis; T. Teijeiro; P. Ryvlin et al.

2022-03-23. Design Automation and Test in Europe Conference (DATE2022), Grenoble, France, March 16-23, 2022.

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A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

I. Scarabottolo; G. Ansaloni; G. A. Constantinides; L. Pozzi

Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems. 2022-04-01. DOI : 10.1109/TCAD.2021.3075651.

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ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

J. A. H. Klein; i. Boybat; Y. M. Qureshi; M. Dazzi; A. S. J. Levisse et al.

arXiv. 2022-04-07.

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Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

M. A. Rios; F. Ponzina; G. Ansaloni; A. S. J. Levisse; D. Atienza Alonso

2022-06-07. Great Lakes Symposium on VLSI 2022 (GLSVLSI ’22), Irvine, California, USA, June 6-8, 2022. DOI : 10.1145/3526241.3530351.

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Giovanni Ansaloni

Publications

Publications Infoscience

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.

Compiling custom instructions onto expression-grained reconfigurable architectures

Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.

Architectural Exploration and Scheduling Methods for Coarse Grained Reconfigurable Arrays

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays

EGRA: A Coarse Grained Reconfigurable Architectural Template

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring

Embedded Real-Time ECG Delineation Methods: a Comparative Evaluation

A Methodology for Embedded Classification of Heartbeats Using Random Projections

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes

Ultra-Low Power Design of Wearable Cardiac Monitoring Systems

Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach

Hardware-Software Inexactness in Noise-aware Design of Low-Power Body Sensor Nodes

Power-Efficient Joint Compressed Sensing of Multi-Lead ECG Signals

Ultra-Low Power Design of Wearable Cardiac Monitoring Systems

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

Method for detecting abnormalities in an electrocardiogram

Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices

Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes

A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications

Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs

DB4HLS: A Database of High-Level Synthesis Design Space Explorations

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

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