Giovanni De Micheli
+41 21 693 09 11
Office:
INF 341
EPFL › VPA › VPA-AVP-CP › ECOCLOUD › ECOCLOUD-GE
Site web: https://ecocloud.ch
+41 21 693 09 11
Office:
INF 341
EPFL › IC › IC-DEC › PH-IC
Site web: https://www.epfl.ch/schools/ic/about/faculty-members/#emeritus
Expertise
En savoir plus
Publications représentatives
Synthesis and Optimization of Digital Circuits
G. De Micheli
Published in McGraw-Hill, 1994.
in
Networks on Chips
G. De Micheli and L. Benini
Published in Morgan Kaufmann, 2006. in
Policy Optimization for Dynamic Power Management
L. Benini, A. Bogliolo, G. Paleologo and G. De Micheli
Published in IEEE Transactions on CAD, Vol. 18, No. 6, June 1999, pp. 813-833. in
Enseignement et PhD
A dirigé les thèses EPFL de
Abhishek Garg (2009), Mohamed Haykel Ben Jamaa (2009), Francesco Zanini (2011), Ciprian Seiculescu (2012), Cristina Boero (2012), Hu Xu (2012), Andrea Cavallini (2013), Shashi Kanth Bobba (2013), Jacopo Olivo (2013), Wenqi You Dubout (2014), Michele De Marchi (2015), Somayyeh Rahimian Omam (2015), Irene Taurino (2015), Camilla Baj-Rossi (2015), Seyedeh Sara Ghoreishizadeh (2015), Luca Gaetano Amarù (2015), Francesca Puppo (2016), Hassan Ghasemzadeh Mohammadi (2016), Jian Zhang (2016), Xifan Tang (2017), Stefanos Skalistis (2017), Aya Mohamed Naguib Ahmed Ibrahim (2018), Giovanni Vincenzo Resta (2019), Winston Jason Haaswijk (2019), Eleonora Testa (2020), Francesca Criscuolo (2020), Mandresy Ivan Ny Hanitra (2021), Giulia Meuli (2021), Bruno Schmitt Antunes (2022), Fereshte Mozafari (2023), Siang-Yun Lee (2024), Alessandro Tempia Calvino (2024), Marakkalage Dewmini Sudara (2025), Andrea Costamagna (2026), Mingfei Yu (2025)
A co-dirigé les thèses EPFL de
Davide Sacchetto (2013), Giulia Beanato (2014), Julien Michel Ghaye (2015), Nima Aliakbari (2017), Ioulia Tzouvadaki (2017), Francesca Stradolini (2018), Lana Josipovic (2021)
Cours
Design technologies for integrated systems
CS-472
La synthèse hardware est le processus de transformation - itérativement raffiné, détaillé et optimisé - d'une représentation faite en langage de description matérielle en un circuit. Ce cours présente les algorithmes, outils et méthodes de la compilation matérielle et de la synthèse logique.