James Larus

EPFL IC-DO
BC 407 (Bâtiment BC)
Station 14
1015 Lausanne

EPFL IC-DO
BC 407 (Bâtiment BC)
Station 14
1015 Lausanne

Expertise

James Larus is a Professor Emeritus and former Dean of the School of Computer and Communication Sciences (IC) at EPFL (école Polytechnique Fédérale de Lausanne). Before joining IC in October 2013, Larus was a researcher, manager, and director in Microsoft Research for over 16 years and an Assistant and Associate Professor in the Computer Sciences Department at the University of Wisconsin, Madison.
Larus has been an active contributor to numerous communities. He published over 100 papers (with 14 best and most influential papers and test-of-time awards), received over 40 US patents, and served on many program committees and NSF, NRC, and DARPA panels. His book, Transactional Memory (Morgan Claypool), appeared in 2007. Larus received a National Science Foundation Young Investigator award in 1993 and became an ACM Fellow in 2006.
At EPFL, Larus co-founded DP3T, which produced the SwissCOVID contract-tracing app and developed the privacy-preserving contract-tracing protocol used by Apple's and Google's Exposure Notification framework. His Very-Large Scale Computing (VLSC) lab studies programming models for non-volatile memory (NVM), programming models for FPGAs, and accelerating bioinformatics computation.
Larus joined Microsoft Research in 1998 to start and lead the Software Productivity Tools (SPT) group, which developed and applied various innovative program analysis techniques to build tools to find software defects. The research community widely recognized this group's ground-breaking research in program analysis and software defect detection. It was shipped in Microsoft products such as the Static Driver Verifier, FX/Cop, and other software development tools. Larus became an MSR Research Area Manager for programming languages and tools. He started the Singularity research project, demonstrating that modern programming languages and software engineering techniques could fundamentally improve software architectures. Subsequently, he helped create XCG, an MSR effort to develop hardware and software support for cloud computing. In XCG, Larus designed the Orleans framework for cloud programming and contributed to the Catapult FPGA accelerator for the Bing search engine.
Before joining Microsoft, Larus was an Assistant and Associate Professor of Computer Science at the University of Wisconsin-Madison. He published over 60 research papers and co-led the Wisconsin Wind Tunnel (WWT) research project with Professors Mark Hill and David Wood. WWT was a DARPA and NSF-funded project investigating innovative approaches to simulating, building, and programming parallel shared-memory computers. Larus's research spanned many areas, including new and efficient techniques for measuring and recording executing programs' behavior, tools for analyzing and manipulating compiled and linked programs, programming languages for parallel computing, tools for verifying program correctness, and techniques for compiler analysis and optimization.
Larus received his MS and Ph.D. in Computer Science from the University of California, Berkeley, in 1989 and an AB in Applied Mathematics from Harvard in 1980. At Berkeley, Larus developed one of the first systems to analyze Lisp programs and determine how to execute them on a parallel computer.
CV

Expertise

James Larus is a Professor Emeritus and former Dean of the School of Computer and Communication Sciences (IC) at EPFL (école Polytechnique Fédérale de Lausanne). Before joining IC in October 2013, Larus was a researcher, manager, and director in Microsoft Research for over 16 years and an Assistant and Associate Professor in the Computer Sciences Department at the University of Wisconsin, Madison.
Larus has been an active contributor to numerous communities. He published over 100 papers (with 14 best and most influential papers and test-of-time awards), received over 40 US patents, and served on many program committees and NSF, NRC, and DARPA panels. His book, Transactional Memory (Morgan Claypool), appeared in 2007. Larus received a National Science Foundation Young Investigator award in 1993 and became an ACM Fellow in 2006.
At EPFL, Larus co-founded DP3T, which produced the SwissCOVID contract-tracing app and developed the privacy-preserving contract-tracing protocol used by Apple's and Google's Exposure Notification framework. His Very-Large Scale Computing (VLSC) lab studies programming models for non-volatile memory (NVM), programming models for FPGAs, and accelerating bioinformatics computation.
Larus joined Microsoft Research in 1998 to start and lead the Software Productivity Tools (SPT) group, which developed and applied various innovative program analysis techniques to build tools to find software defects. The research community widely recognized this group's ground-breaking research in program analysis and software defect detection. It was shipped in Microsoft products such as the Static Driver Verifier, FX/Cop, and other software development tools. Larus became an MSR Research Area Manager for programming languages and tools. He started the Singularity research project, demonstrating that modern programming languages and software engineering techniques could fundamentally improve software architectures. Subsequently, he helped create XCG, an MSR effort to develop hardware and software support for cloud computing. In XCG, Larus designed the Orleans framework for cloud programming and contributed to the Catapult FPGA accelerator for the Bing search engine.
Before joining Microsoft, Larus was an Assistant and Associate Professor of Computer Science at the University of Wisconsin-Madison. He published over 60 research papers and co-led the Wisconsin Wind Tunnel (WWT) research project with Professors Mark Hill and David Wood. WWT was a DARPA and NSF-funded project investigating innovative approaches to simulating, building, and programming parallel shared-memory computers. Larus's research spanned many areas, including new and efficient techniques for measuring and recording executing programs' behavior, tools for analyzing and manipulating compiled and linked programs, programming languages for parallel computing, tools for verifying program correctness, and techniques for compiler analysis and optimization.
Larus received his MS and Ph.D. in Computer Science from the University of California, Berkeley, in 1989 and an AB in Applied Mathematics from Harvard in 1980. At Berkeley, Larus developed one of the first systems to analyze Lisp programs and determine how to execute them on a parallel computer.
CV

Very Large Scale Computing Lab

My blog

Blog about various technical and Switzerland related topics.

Talks

Link to recent public talks.

James Larus's Publications

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

S. Kashani / J. R. Larus (Dir.)

Lausanne, EPFL, 2023. DOI : 10.5075/epfl-thesis-8990.

Deploying Decentralized, Privacy-Preserving Proximity Tracing

C. TroncosoD. BogdanovE. BugnionS. ChatelC. Cremers  et al.

Communications Of The Acm. 2022. DOI : 10.1145/3524107.

Whose Smartphone Is It?

J. R. Larus

Communications Of The ACM. 2021. DOI : 10.1145/3454007.

Enclosure: Language-Based Restriction of Untrusted Libraries

A. GhosnM. KogiasM. PayerJ. LarusE. Bugnion

2021. ASPLOS 21, Virtual Conference, April 19-23, 2021. p. 255 - . DOI : 10.1145/3445814.3446728.

Software Support for Non-Volatile Memory (NVM) Programming

D. T. Aksun / J. R. Larus (Dir.)

Lausanne, EPFL, 2021. DOI : 10.5075/epfl-thesis-7187.

Abacus: Precise Side-Channel Analysis

Q. BaoZ. WangX. LiJ. R. LarusD. Wu

2021. 43rd IEEE/ACM International Conference on Software Engineering - Software Engineering in Practice (ICSE-SEIP) / 43rd ACM/IEEE International Conference on Software Engineering - New Ideas and Emerging Results (ICSE-NIER), ELECTR NETWORK, May 25-28, 2021. p. 797 - 809. DOI : 10.1109/ICSE43902.2021.00078.

Abacus: A Tool for Precise Side-channel Analysis

Q. BaoZ. WangJ. R. LarusD. Wu

2021. IEEE/ACM 43rd International Conference on Software Engineering (ICSE), ELECTR NETWORK, May 25-28, 2021. p. 238 - 239. DOI : 10.1109/ICSE-Companion52605.2021.00110.

Early evidence of effectiveness of digital contact tracing for SARS-CoV-2 in Switzerland

M. SalatheC. L. AlthausN. AndereggD. AntonioliT. Ballouz  et al.

Swiss Medical Weekly. 2020. DOI : 10.4414/smw.20457.

Parallel and Scalable Precise Clustering

S. BymaA. DhasadeA. AltenhoffC. DessimozJ. R. Larus

2020. ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), ELECTR NETWORK, Oct 03-07, 2020. p. 217 - 228. DOI : 10.1145/3410463.3414646.

Parallel and Scalable Bioinformatics

S. A. Byma / J. R. Larus (Dir.)

Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10141.

Fine-Grain Checkpointing with In-Cache-Line Logging

N. CohenD. T. AksunJ. Larus

2019. 2019 Architectural Support for Programming Languages and Operating Systems (ASPLOS ’19), Providence, RI USA, April 13-17. DOI : 10.1145/3297858.3304046.

IMPACT: Interval-based Multi-pass Proteomic Alignment with Constant Traceback

S. Kashani-AkhavanS. A. BymaJ. Larus

2019. 2nd HPCA Workshop on Accelerator Architectures in Computational Biology and Bioinformatics, Washington, DC USA, February 16, 2019.

Secured Routines: Language-based Construction of Trusted Execution Environments

A. GhosnJ. LarusE. Bugnion

2019. USENIX Annual Technical Conference 2019, Renton, WA, USA, July 10-12, 2019. p. 571 - 585.

WOK: Statistical Program Slicing in Production

B.-A. StoicaS. K. SahooJ. R. LarusV. S. Adve

2019. IEEE/ACM 41st International Conference on Software Engineering - Software Engineering in Practice (ICSE-SEIP), Montreal, CANADA, May 25-31, 2019. p. 324 - 325. DOI : 10.1109/ICSE-Companion.2019.00136.

Object-Oriented Recovery for Non-volatile Memory

N. CohenD. T. AksunJ. Larus

2018. Object-Oriented Programming, Systems, Languages, and Applications - OOPSLA 2018, Boston, MA, USA, November 7-9, 2018. DOI : 10.1145/3276523.

Detailed Heap Profiling

S. A. BymaJ. Larus

2018. International Symposium on Memory Management (ISMM 2018), Philadelphia, PA, USA, June 18, 2018. p. 1 - 13. DOI : 10.1145/3210563.3210564.

POSTER: Reducing Transaction Aborts by Looking to the Future

N. CohenE. PetrankJ. R. Larus

2018. 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Vienna, AUSTRIA, Feb 24-28, 2018. p. 385 - 386. DOI : 10.1145/3178487.3178518.

A Simple, Elegant Approach to Non-Numeric Parallelization

J. Larus

Communications Of The ACM. 2017. DOI : 10.1145/3139459.

Efficient Logging in Non-Volatile Memory by Exploiting Coherency Protocols

N. CohenM. FriedmanJ. R. Larus

2017. SPLASH 2017 OOPSLA, Vancouver, Canada, October 25-27, 2017. DOI : 10.1145/3133891.

Persona: A High-Performance Bioinformatics Framework

S. A. BymaS. D. WhitlockL. FlueratoruE. TsengC. Kozyrakis  et al.

2017. USENIX Annual Technical Conference 2017, Santa Clara, California, USA, July 12-14, 2017.

Technical Perspective: The Power of Parallelizing Computations

J. Larus

Communications Of The ACM. 2016. DOI : 10.1145/2985782.

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

A. PutnamA. M. CaulfieldE. S. ChungD. ChiouK. Constantinides  et al.

Communications Of The ACM. 2016. DOI : 10.1145/2996868.

A Reconfigurable Fabric For Accelerating Large-Scale Datacenter Services

A. PutnamA. M. CaulfieldE. S. ChungD. ChiouK. Constantinides  et al.

IEEE Micro. 2015. DOI : 10.1109/MM.2015.42.

Technical Perspective Programming Multicore Computers

J. Larus

Communications Of The ACM. 2015. DOI : 10.1145/2742910.

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

A. PutnamA. M. CaulfieldE. S. ChungD. ChiouK. Constantinides  et al.

2014. 2014 ACM/IEEE 41st International Symposium on Computer Architecture, Minneapolis, MN, 14-18 June 2014. p. 13 - 24. DOI : 10.1109/ISCA.2014.6853195.

SIMD Parallelization of Applications that Traverse Irregular Data Structures

B. RenG. AgrawalJ. R. LarusT. MytkowiczT. Poutanen  et al.

2013. p. 1 - 10. DOI : 10.1109/CGO.2013.6494989.

Look up!: Your Future is in the Cloud

J. R. Larus

2013. p. 1 - 2. DOI : 10.1145/2462156.2462157.

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

T. GaoK. StraussS. M. BlackburnK. S. McKinleyD. Burger  et al.

2013. p. 297 - 308. DOI : 10.1145/2462156.2462171.

It's the End of the World as We Know It (And I Feel Fine)

J. R. Larus

2012. p. 48 - 48. DOI : 10.1007/978-3-642-35632-2_7.

Fine-grained Parallel Traversals of Irregular Data Structures

B. RenG. AgrawalJ. R. LarusT. MytkowiczT. Poutanen  et al.

2012. p. 461 - 462. DOI : 10.1145/2370816.2370896.

Zeta: Scheduling Interactive Services with Partial Execution

Y. HeS. ElniketyJ. LarusC. Yan

2012. p. 1 - 14. DOI : 10.1145/2391229.2391241.

Imagining the Future: Thoughts on Computing

D. A. ReedD. B. GannonJ. R. Larus

IEEE Computer. 2012. DOI : 10.1109/MC.2011.327.

The Cloud Will Change Everything

J. R. Larus

2011. p. 1 - 2. DOI : 10.1145/1961295.1950367.

Orleans: Cloud Computing for Everyone

S. BykovA. GellerG. KliotJ. R. LarusR. Pandya  et al.

2011. p. 1 - 14. DOI : 10.1145/2038916.2038932.

Programming the Cloud

J. R. Larus

2011. p. 1 - 2. DOI : 10.1145/1941553.1941555.

Join-Idle-Queue: A Novel Load Balancing Algorithm for Dynamically Scalable Web Services

Y. LuQ. XieG. KliotA. GellerJ. R. Larus  et al.

Performance Evaluation. 2011. DOI : 10.1016/j.peva.2011.07.015.

Transactional Memory: 2nd edition

T. HarrisJ. LarusR. Rajwar

Morgan & Claypool, 2010.

The Singularity System

J. LarusG. Hunt

Communications of the ACM. 2010. DOI : 10.1145/1787234.1787253.

Spending Moore's Dividend

J. Larus

Communications of the ACM. 2009. DOI : 10.1145/1506409.1506425.

Multicore Computing and Scientific Discovery

J. LarusD. Gannon

The Fourth Paradigm: Data-Intensive Scientific Discovery; Microsoft Research, 2009. p. 125 - 130.

Transactional Memory

J. LarusC. Kozyrakis

Communications of the ACM. 2008. DOI : 10.1145/1364782.1364800.

Spending Moore's Dividend

J. R. Larus

2008

PL Research and its Consequences on PL Curriculum

J. Larus

ACM SIGPLAN Notices. 2008. DOI : 10.1145/1480828.1480847.

The Real Value of Testing

J. Larus

2008. p. 1 - 2. DOI : 10.1145/1390630.1390631.

Sealing OS Processes to Improve Dependability and Safety

G. HuntM. AikenM. FähndrichC. HawblitzelO. Hodson  et al.

2007. p. 341 - 354. DOI : 10.1145/1272996.1273032.

Singularity: Rethinking the Software Stack

G. HuntJ. Larus

ACM SIGOPS Operating Systems Review. 2007. DOI : 10.1145/1243418.1243424.

Corezilla: Build and Tame the Multicore Beast?

L. SarnoW.-m. W. HwuC. LundM. LevyJ. R. Larus  et al.

2007. p. 632 - 633. DOI : 10.1109/DAC.2007.375240.

Featherweight Transactions: Decoupling Threads and Atomic Blocks

V. J. MaratheT. HarrisJ. R. Larus

2007. p. 134 - 135. DOI : 10.1145/1229428.1229453.

Singularity

J. LarusG. HuntD. Tarditi

MSDN Magazine. 2006.

Foreward to Programming Language Pragmatics

J. R. Larus

Programming Language Pragmatics; Elsevier, 2006.

Abolish Runtime Systems: Operating Systems Should Control the Execution

J. R. Larus

2006. DOI : 10.1145/1134760.1134761.

Reflective Program Teneration with Patterns

M. FähndrichM. CarbinJ. R. Larus

2006. p. 275 - 284. DOI : 10.1145/1173706.1173748.

Deconstructing Process Isolation

M. AikenM. FähndrichC. HawblitzelG. HuntJ. R. Larus

2006. p. 1 - 10. DOI : 10.1145/1178597.1178599.

Is Process or Architecture the Solution?

J. Larus

2006. DOI : 10.1145/1181309.1181310.

Transactional Memory

J. R. LarusR. Rajwar

Morgan & Claypool, 2006.

Language Support for Fast and Reliable Message Based Communication in Singularity OS

M. FähndrichM. AikenC. HawblitzelO. HodsonG. Hunt  et al.

2006. p. 177 - 190. DOI : 10.1145/1217935.1217953.

Broad New OS Research: Challenges and Opportunities

G. C. HuntJ. R. LarusD. TarditiT. Wobber

2005.

Software and the Concurrency Revolution

H. SutterJ. Larus

ACM Queue. 2005. DOI : 10.1145/1095408.1095421.

An Overview of the Singularity Project

G. HuntJ. LarusM. AbadiM. AikenP. Barham  et al.

2005

Foreword to Why Programs Fail: A Guide to Systematic Debugging

J. R. Larus

Why Programs Fail: A Guide to Systematic Debugging; Elsevier, 2005. p. xix - xx.

Righting Software

J. R. LarusT. BallM. DasR. DeLineM. Fähndrich  et al.

IEEE Software. 2004. DOI : 10.1109/MS.2004.1293079.

Debugging Temporal Specifications with Concept Analysis

G. AmmonsD. MandelinR. BodíkJ. R. Larus

2003. p. 182 - 195. DOI : 10.1145/781131.781152.

Using Cohort-Scheduling to Enhance Server Performance

J. R. LarusM. Parkes

2002. p. 103 - 114.

Mining Specifications

G. AmmonsR. BodikJ. R. Larus

2002. p. 4 - 16. DOI : 10.1145/503272.503275.

Behavioral Types for Structured Asynchronous Programming

J. R. LarusS. K. RajamaniJ. Rehof

2001

Facile: A Language and Compiler for High-performance Processor Simulators

E. C. SchnarrM. D. HillJ. R. Larus

2001. p. 321 - 331. DOI : 10.1145/378795.378864.

Using Cohort Scheduling to Enhance Server Performance (Extended Abstract)

J. R. LarusM. Parkes

2001. p. 182 - 187. DOI : 10.1145/384197.384222.

Using Paths to Measure, Explain, and Enhance Program Behavior

T. BallJ. R. Larus

IEEE Computer. 2000. DOI : 10.1109/2.869371.

Making Pointer-Based Data Structures Cache Conscious

T. M. ChilimbiM. D. HillJ. R. Larus

IEEE Computer. 2000. DOI : 10.1109/2.889095.

Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator

S. S. MukherjeeS. K. ReinhardtB. FalsafiM. LitzkowM. D. Hill  et al.

IEEE Concurrency. 2000. DOI : 10.1109/4434.895100.

Programs Follow Paths

T. BallJ. R. Larus

1999

Cache-Conscious Structure Layout

T. M. ChilimbiJ. R. LarusM. D. Hill

1999. p. 1 - 12. DOI : 10.1145/301618.301633.

Teapot: A Domain-Specific Language for Writing Cache Coherence Protocols

S. ChandraB. RichardsJ. R. Larus

IEEE Transactions on Software Engineering. 1999. DOI : 10.1109/32.798322.

Cache-Conscious Structure Definition

T. M. ChilimbiB. DavidsonJ. R. Larus

1999. p. 13 - 25. DOI : 10.1145/301618.301635.

Whole Program Paths

J. R. Larus

1999. p. 259 - 269. DOI : 10.1145/301618.301678.

Fast Out-of-order Processor Simulation Using Memoization

E. SchnarrJ. R. Larus

1998. p. 283 - 294. DOI : 10.1145/291069.291063.

Improving Data-flow Analysis with Path Profiles

G. AmmonsJ. R. Larus

1998. p. 72 - 84. DOI : 10.1145/989393.989451.

Using Generational Garbage Collection to Implement Cache-Conscious Data Placement

T. M. ChilimbiJ. R. Larus

1998. p. 36 - 48. DOI : 10.1145/286860.286865.

Sirocco: cost-effective fine-grain distributed shared memory

I. SchoinasB. FalsafiM. D. HillJ. R. LarusD. A. Wood

1998. p. 40 - 49. DOI : 10.1109/PACT.1998.727144.

Protocol-based Data-race Detection

B. RichardsJ. R. Larus

1998. p. 40 - 47. DOI : 10.1145/281035.281040.

Retrospective: Tempest and Typhoon: User-level Shared Memory

S. K. ReinhardtJ. R. LarusD. A. Wood

1998. p. 98 - 102. DOI : 10.1145/285930.285968.

Shared-Memory Performance Profiling

Z. XuJ. R. LarusB. P. Miller

1997. p. 240 - 251. DOI : 10.1145/263764.263796.

Wisconsin Wind Tunnel II: A Fast and Portable Parallel Architecture Simulator

S. S. MukherjeeS. K. ReinhardtB. FalsafiM. LitzkowS. Huss-Lederman  et al.

1997.

Fine-grain Access Control for Distributed Shared Memory

I. SchoinasB. FalsafiA. R. LebeckS. K. ReinhardtJ. R. Larus  et al.

Distributed Shared Memory: Concepts and Systems; IEEE Computer Society Press, 1997.

The Use of Program Profiling for Software Maintenance with Applications to the Year 2000 Problem

T. RepsT. BallM. DasJ. R. Larus

1997. p. 432 - 449. DOI : 10.1145/267895.267925.

HPF on Fine-Grain Distributed Shared Memory: Early Experience

S. ChandraJ. R. Larus

1997. 9th International Workshop, LCPC'96, San Jose, California, USA, August 8–10, 1996. p. 450 - 465. DOI : 10.1007/BFb0017269.

Exploiting Hardware Performance Counters with Flow and Context Sensitive Profiling

G. AmmonsT. BallJ. R. Larus

1997. p. 85 - 96. DOI : 10.1145/258915.258924.

Optimizing Communication in HPF programs for Fine-Grain Distributed Shared Memory

S. ChandraJ. R. Larus

1997. p. 100 - 111. DOI : 10.1145/263764.263780.

Experience with a Language for Writing Coherence Protocols

S. ChandraM. DahlinB. RichardsR. Y. WangT. E. Anderson  et al.

1997. p. 51 - 66.

Instruction Scheduling and Executable Editing

E. SchnarrJ. R. Larus

1996. 29th International Symposium on Microarchitecture, Paris, France, 2-4 Dec. 1996. p. 288 - 297. DOI : 10.1109/MICRO.1996.566469.

Teapot: Language Support for Writing Memory Coherence Protocols

S. ChandraB. RichardsJ. R. Larus

1996. p. 237 - 248. DOI : 10.1145/231379.231430.

The Tempest Approach to Distributed Shared Memory

D. A. WoodM. D. HillJ. R. Larus

1996. p. 63 - 64. DOI : 10.1109/ICCD.1996.563534.

Implementing Fine-grain Distributed Shared Memory on Commodity SMP Workstations

I. SchoinasB. FalsafiM. D. HillJ. R. LarusC. E. Lukas  et al.

1996

Compiler-directed Shared-Memory Communication for Iterative Parallel Applications

G. ViswanathanJ. R. Larus

1996. DOI : 10.1145/369028.369047.

Instruction Scheduling and Executable Editing (prelim)

E. SchnarrJ. R. Larus

1996.

Parallel Computer Research in the Wisconsin Wind Tunnel Project

M. D. HillJ. R. LarusD. A. Wood

1996. p. 135 - 145.

Parallel Programming in C**: A Large-Grain Data-Parallel Programming Language

J. R. LarusB. RichardsG. Viswanathan

Parallel Programming Using C++; MIT Press, 1996. p. 297 - 342.

Efficient Path Profiling

T. BallJ. R. Larus

1996. 29th International Symposium on Microarchitecture. p. 46 - 57. DOI : 10.1109/MICRO.1996.566449.

Portably Supporting Parallel Programming Languages

M. HillJ. LarusD. Wood

IEEE Computer. 1995.

Why Write Real Software in a University?

J. R. Larus

1995. DOI : 10.1145/1275165.1275166.

StormWatch: A Tool for Visualizing Memory System Protocols

T. ChilimbiT. BallS. EickJ. Larus

1995. DOI : 10.1145/224170.224287.

Efficient Support for Irregular Applications on Distributed-Memory Machines

S. S. MukherjeeS. D. SharmaM. D. HillJ. R. LarusA. Rogers  et al.

1995. p. 68 - 79. DOI : 10.1145/209936.209945.

Tempest: A Substrate for Portable Parallel Programs

M. D. HillJ. R. LarusD. A. Wood

1995. p. 327 - 332. DOI : 10.1109/CMPCON.1995.512404.

EEL: Machine-Independent Executable Editing

J. R. LarusE. Schnarr

1995. p. 291 - 300. DOI : 10.1145/207110.207163.

The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers

S. K. ReinhardtM. D. HillJ. R. LarusA. R. LebeckJ. C. Lewis  et al.

Multiprocessor Performance Measurement and Evaluation; IEEE, 1994. p. 150 - 162.

Using the Run-Time Sizes of Data Structures to Guide Parallel-Thread Creation

L. HuelsbergenJ. R. LarusA. Aiken

1994. p. 79 - 90. DOI : 10.1145/182409.182442.

Static Branch Frequency and Program Profile Analysis

Y. WuJ. R. Larus

1994. p. 1 - 11. DOI : 10.1145/192724.192725.

CICO: A Practical Shared-Memory Programming Performance Model

J. R. LarusS. ChandraD. A. Wood

Portability and Performance for Parallel Processing; John Wiley & Sons Ltd, 1994. p. 99 - 119.

Where is Time Spent in Message-Passing and Shared-Memory Programs?

S. ChandraJ. R. LarusA. Rogers

1994. p. 61 - 75. DOI : 10.1145/381792.195501.

The Wisconsin Wind Tunnel Project: An Annotated Bibliography

M. D. HillJ. R. LarusD. A. Wood

ACM SIGARCH Computer Architecture News. 1994. DOI : 10.1145/192537.192543.

Application-specific protocols for user-level shared memory

B. FalsafiA. R. LebeckS. K. ReinhardtI. SchoinasM. D. Hill  et al.

1994. Supercomputing '94, Washington D.C., USA, November 14-18. p. 380 - 389. DOI : 10.1109/SUPERC.1994.344301.

Cachier: A Tool for Automatically Inserting CICO Annotations

T. M. ChilimbiJ. R. Larus

1994. p. 89 - 98. DOI : 10.1109/ICPP.1994.65.

Rewriting Executable Files to Measure Program Behavior

J. R. LarusT. Ball

Software: Practice and Experience. 1994. DOI : 10.1002/spe.4380240204.

Tempest and Typhoon: User-Level Shared Memory

S. K. ReinhardtJ. R. LarusD. A. Wood

1994. p. 325 - 337. DOI : 10.1145/191995.192062.

Fine-grain access control for distributed shared memory

I. SchoinasB. FalsafiA. R. LebeckS. K. ReinhardtJ. R. Larus  et al.

1994. ASPLOS'94. 6th International Conference on Architectural support for Programming Languages and Operating Systems, San Jose, CA, October. p. 297 - 306. DOI : 10.1145/195470.195575.

LCM: Memory System Support for Parallel Language Implementation

J. R. LarusB. RichardsG. Viswanathan

1994. p. 208 - 218. DOI : 10.1145/195473.195545.

Mechanisms for Cooperative Shared Memory

D. A. WoodS. ChandraB. FalsafiM. D. HillJ. R. Larus  et al.

CMG Transactions. 1994. DOI : 10.1145/173682.165151.

Optimally Profiling and Tracing Programs

T. BallJ. R. Larus

ACM Transactions on Programming Languages and Systems. 1994. DOI : 10.1145/183432.183527.

The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers

S. K. ReinhardtM. D. HillJ. R. LarusA. R. LebeckJ. C. Lewis  et al.

1993. p. 48 - 60. DOI : 10.1145/166955.166979.

Wisconsin Architectural Research Tool Set

M. D. HillJ. R. LarusA. R. LebeckM. TalluriD. A. Wood

ACM SIGARCH Computer Architecture News. 1993. DOI : 10.1145/165496.165500.

A Concurrent Copying Garbage Collector for Languages that Distinguish (Im)mutable Data

L. HuelsbergenJ. Larus

1993. p. 73 - 82. DOI : 10.1145/155332.155340.

Mechanisms for cooperative shared memory

D. A. WoodS. ChandraB. FalsafiM. D. HillJ. R. Larus  et al.

1993. 20th International Symposium on Computer Architecture, San Diego, CA, May. p. 156 - 167. DOI : 10.1145/165123.165151.

C**: a Large-Grain, Object-Oriented, Data-Parallel Programming Language

J. R. Larus

1993. p. 326 - 341. DOI : 10.1007/3-540-57502-2_56.

Assemblers, Linkers, and the SPIM Simulator

J. R. Larus

Computer Organization & Design: The Hardware/Software Interface; Morgan Kaufmann, 1993.

Using Tracing and Dynamic Slicing to Tune Compilers

J. R. LarusS. Chandra

1993

Branch Prediction for Free

T. BallJ. R. Larus

1993. p. 300 - 313. DOI : 10.1145/155090.155119.

Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors

M. D. HillJ. R. LarusS. K. ReinhardtD. A. Wood

ACM Transactions on Computer Systems. 1993. DOI : 10.1145/161541.161544.

Loop-Level Parallelism in Numeric and Symbolic Programs

J. R. Larus

IEEE Transactions on Parallel and Distributed Systems. 1993. DOI : 10.1109/71.238302.

Compiling for Shared-Memory and Message-Passing Computers

J. R. Larus

ACM Letters on Programming Languages and Systems. 1993. DOI : 10.1145/176454.176514.

Efficient Program Tracing

J. R. Larus

IEEE Computer. 1993. DOI : 10.1109/2.211900.

Optimally Profiling and Tracing Programs

T. BallJ. R. Larus

1992. p. 59 - 70. DOI : 10.1145/143165.143180.

Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors

M. D. HillJ. R. LarusS. K. ReinhardtD. A. Wood

1992. p. 262 - 273. DOI : 10.1145/143365.143537.

Dynamic Program Parallelization

L. HuelsbergenJ. R. Larus

1992. p. 331 - 323. DOI : 10.1145/141471.141567.

Estimating the Potential Parallelism in Programs

J. R. Larus

1991. p. 331 - 349.

Compiling Lisp Programs for Parallel Execution

J. R. Larus

Lisp and Symbolic Computation. 1991. DOI : 10.1007/BF01806061.

Abstract Execution: A Technique for Efficiently Tracing Programs

J. R. Larus

Software-Practice and Experience. 1990. DOI : 10.1002/spe.4380201205.

Predicting the Effects of Optimization on Parallel Programs

J. R. Larus

1990

Cache Considerations for Programmers of Multiprocessors

M. D. HillJ. R. Larus

Communications of the ACM. 1990. DOI : 10.1145/79173.79180.

Exact Data Dependence Analysis Using Data Access Descriptors (Extended Abstract)

L. HuelsbergenD. HahnJ. Larus

1990. p. 290 - 291.

Design Decisions in SPUR

M. D. HillS. J. EggersJ. R. LarusG. S. Taylor

Computers for Artificial Intelligence Processing; John Wiley & Sons, 1990. p. 273 - 299.

Exact Data Dependence Analysis Using Data Access Descriptors

L. HuelsbergenD. HahnJ. Larus

1990

Evaluation of Acuff's Lisp Benchmarks

J. Larus

1989

Restructuring Symbolic Programs for Concurrent Execution on Multiprocessors

J. R. Larus (Dir.)

Computer Science Division (EECS), University of California at Berkeley, 1989.

Lisp Extensions for Multiprocessing

B. G. ZornK. HoJ. LarusL. SemenzatoP. Hilfinger

1989. p. 761 - 770. DOI : 10.1109/HICSS.1989.48084.

Multiprocessing Extensions in SPUR Lisp

B. ZornK. HoJ. LarusL. SemenzatoP. Hilfinger

IEEE Computer. 1989. DOI : 10.1109/52.31651.

Restructuring Lisp Programs for Concurrent Execution

J. R. LarusP. N. Hilfinger

1988. p. 100 - 110. DOI : 10.1145/62115.62126.

Features for Multiprocessing in SPUR Lisp

B. ZornP. HilfingerK. HoJ. LarusL. Semenzato

1988

Detecting Conflicts Between Structure Accesses

J. R. LarusP. N. Hilfinger

1988. p. 21 - 34. DOI : 10.1145/53990.53993.

SPUR Lisp: Design and Implementation

B. ZornP. HilfingerK. HoJ. Larus

1987

An Interactive Program Analysis System for Franz Lisp

J. R. Larus / R. Fateman (Dir.)

University of California, 1987.

Curare: Restructuring Lisp Programs for Concurrent Execution

J. R. Larus

1987

Evaluation of the SPUR Lisp Architecture

G. S. TaylorP. N. HilfingerJ. R. LarusD. A. PattersonB. G. Zorn

1986. p. 444 - 452. DOI : 10.1145/17407.17379.

Register Allocation in the SPUR Lisp Compiler

J. R. LarusP. N. Hilfinger

1986. p. 255 - 263. DOI : 10.1145/12276.13337.

Design Decisions in SPUR

M. D. HillS. J. EggersJ. R. LarusG. S. Taylor

IEEE Computer. 1986. DOI : 10.1109/MC.1986.1663096.

Priority Queues on the Butterfly Multiprocessor

J. Larus

1984

Using the Baskett Test as a Benchmark for the Butterfly Multiprocessor

J. Larus

1984

Parlez-Vous Franz? An Informal Introduction to Interfacing Foreign Functions to Franz LISP

J. Larus

1983

Classy: A Method for Efficiently Compiling Smalltalk

J. LarusW. Bush

1983

On the Performance of Courier Remote Procedure Calls Under 4.1c Berkeley Unix

J. Larus

1983

A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I

J. R. Larus

ACM SIGARCH Computer Architecture News. 1982. DOI : 10.1145/641559.641561.

Research

Very Large Scale Computing Laboratory

Very Large Scale Computing Laboratory

Teaching & PhD

Past EPFL PhD Students

Stuart Anthony Byma, David Teksen Aksun, Sahand Kashani

Past EPFL PhD Students as codirector

Adrien Ghosn, Seyedmahyar Emami