Marco Mattavelli
Maître d'enseignement et de recherche
marco.mattavelli@epfl.ch +41 21 693 69 84 http://gramm.epfl.ch/
Nationalité : Italian and Swiss
Date de naissance : 18.07.1961
EPFL SCI STI MM
ELB 141 (Bâtiment ELB)
Station 11
CH-1015 Lausanne
+41 21 693 69 84
+41 21 693 69 81
Local: ELB 141
EPFL > STI > IEL > SCI-STI-MM
Web site: Site web: https://gramm.epfl.ch/
+41 21 693 69 84
EPFL > STI > STI-SEL > SEL-ENS
Publications
Publications Infoscience
Fully Soft-Switched High Step-Up Nonisolated Three-Port DC-DC Converter Using GaN HEMTs
Ieee Transactions On Industrial Electronics. 2020-10-01. DOI : 10.1109/TIE.2019.2944068.Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2020-07-11. DOI : 10.1007/s11265-020-01568-5.High Precision Capacitive Moisture Sensor for Polymers: Modeling and Experiments
IEEE Sensors Journal. 2020-03-15. DOI : 10.1109/JSEN.2019.2957108.Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10353.Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism
2019-06-08. Computational Science – ICCS 2019. p. 717-724. DOI : 10.1007/978-3-030-22750-0_70.Low-Cost Readout Electronics for Piezoresistive MEMS-Based Transducers
2019-01-01. IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Auckland, NEW ZEALAND, May 20-23, 2019. p. 1597-1601.On the relevance of quality score metadata in genomic sequence data for omics applications
Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9812.A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System
2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 261-264.An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms
2019-01-01. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1537-1541. DOI : 10.1109/ICASSP.2019.8682525.Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements
2019-01-01. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100-103.Toward a Dynamic Threshold for Quality-Score Distortion in Reference-Based Alignment
2019. 15th International Symposium on Bioinformatics Research and Applications (ISBRA), Barcelona, Spain, June 3–6, 2019.Execution Trace Graph of Dataflow Process Networks
Ieee Transactions On Multi-Scale Computing Systems. 2018-07-01. DOI : 10.1109/TMSCS.2018.2790921.Shared-variable Synchronization Approaches for Dynamic Data Flow Programs
2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263-268.Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines
2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337-342.High Precision Capacitive Moisture Sensor for Polymers
2018-01-01. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212-215.Visual speech recognition
Lausanne, EPFL, 2018. DOI : 10.5075/epfl-thesis-8799.Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis
2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.Transcriptome reconstruction with quality score distortion in reference-based alignment
Research in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs
IEEE Transactions on Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2017.2774294.Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS)
2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms
2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.High level synthesis of Smith-Waterman dataflow implementations
2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.MPEG-G the emerging standard for genomic data compression
2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.Differential gene expression with lossy compression of quality scores in RNA-seq data
2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7649.Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.Trace-based manycore partitioning of stream-processing applications
2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.High-level system synthesis and optimization of dataflow programs for MPSoCs
2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. DOI : 10.1109/TCAD.2016.2597215.High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling
Journal of Signal Processing Systems. 2016-03-05. DOI : 10.1007/s11265-016-1113-x.Comparison of high-throughput sequencing data compression tools
Nature Methods. 2016. DOI : 10.1038/nmeth.4037.An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values
2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs
Journal of Electrical and Computer Engineering. 2016-01-01. DOI : 10.1155/2016/8536432.Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.Automated Design Flow for Multi-Functional Dataflow-Based Platforms
Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.Analysis and optimization of dynamic dataflow programs
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.Actor Merging for Dataflow Process Networks
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.High-level synthesis of dataflow programs for heterogeneous platforms
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.TURNUS: an open-source design space exploration framework for dynamic stream programs
2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.MPEG high efficient video coding stream programming and many-cores scalability
2014.TURNUS: An open-source design space exploration framework for dynamic stream programs
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.Coarse grain clock gating of streaming applications in programmable logic implementations
2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.Characterizing communication behavior of dataflow programs using trace analysis
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms
2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations
2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.ECMA-407: A New 3D audio codec implementation up to NHK 22.2
2014. The 28th VDT International Convention 2014.ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL
2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6112.Optimizing Dataflow Programs for Hardware Synthesis
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http
2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures
2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.Methods to explore design space for MPEG RMC codec specifications
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.Reconfigurable media coding: An overview
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.Synthesis And Optimization Of High-Level Stream Programs
2013. 3rd Electronic System Level Synthesis Conference (ESLsyn), Austin, TX, MAY 31-JUN 01, 2013.Modeling Control Tokens for Composition of CAL Actors
2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS
2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624.Systems Design Space Exploration by Serial Dataflow Program Executions
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures
2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study
2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.Porting an MPEG-HEVC decoder to a low-power many-core platform
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.High-Level Synthesis of Dataflow Programs for Signal Processing Systems
2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.TURNUS: A design exploration framework for dataflow system design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.Synthesis and optimization of high-level stream programs
2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.Buffer optimization based on critical path analysis of a dataflow program design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.Live demonstration: High level software and hardware synthesis of dataflow programs
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.Secure Computing with the MPEG RVC Framework
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.Performance Benchmarking of RVC based Multimedia Specifications
2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem
2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.Representing Guard Dependencies in Dataflow Execution Traces
2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP
2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.Scheduling of dynamic dataflow programs based on state space analysis
2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.Profiling of Dataflow Programs Using Post Mortem Causation Traces
2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program
2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs
Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0396-6.Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs
2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework
2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.Scheduling of Dynamic Dataflow Programs with Model Checking
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.Methodology for the Hardware/Software Co-Design of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.MPEG Reconfigurable Video Representation
The MPEG Representation of Digital Media; Springer, 2011.Infoscience
Fully Soft-Switched High Step-Up Nonisolated Three-Port DC-DC Converter Using GaN HEMTs
Ieee Transactions On Industrial Electronics. 2020-10-01. DOI : 10.1109/TIE.2019.2944068.Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2020-07-11. DOI : 10.1007/s11265-020-01568-5.High Precision Capacitive Moisture Sensor for Polymers: Modeling and Experiments
IEEE Sensors Journal. 2020-03-15. DOI : 10.1109/JSEN.2019.2957108.Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing
Lausanne, EPFL, 2020. DOI : 10.5075/epfl-thesis-10353.Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism
2019-06-08. Computational Science – ICCS 2019. p. 717-724. DOI : 10.1007/978-3-030-22750-0_70.Low-Cost Readout Electronics for Piezoresistive MEMS-Based Transducers
2019-01-01. IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Auckland, NEW ZEALAND, May 20-23, 2019. p. 1597-1601.On the relevance of quality score metadata in genomic sequence data for omics applications
Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9812.A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System
2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 261-264.An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms
2019-01-01. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1537-1541. DOI : 10.1109/ICASSP.2019.8682525.Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements
2019-01-01. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100-103.Toward a Dynamic Threshold for Quality-Score Distortion in Reference-Based Alignment
2019. 15th International Symposium on Bioinformatics Research and Applications (ISBRA), Barcelona, Spain, June 3–6, 2019.Execution Trace Graph of Dataflow Process Networks
Ieee Transactions On Multi-Scale Computing Systems. 2018-07-01. DOI : 10.1109/TMSCS.2018.2790921.Shared-variable Synchronization Approaches for Dynamic Data Flow Programs
2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263-268.Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines
2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337-342.High Precision Capacitive Moisture Sensor for Polymers
2018-01-01. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212-215.Visual speech recognition
Lausanne, EPFL, 2018. DOI : 10.5075/epfl-thesis-8799.Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis
2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.Transcriptome reconstruction with quality score distortion in reference-based alignment
Research in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs
IEEE Transactions on Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2017.2774294.Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS)
2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms
2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.High level synthesis of Smith-Waterman dataflow implementations
2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.MPEG-G the emerging standard for genomic data compression
2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.Differential gene expression with lossy compression of quality scores in RNA-seq data
2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7649.Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.Trace-based manycore partitioning of stream-processing applications
2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.High-level system synthesis and optimization of dataflow programs for MPSoCs
2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. DOI : 10.1109/TCAD.2016.2597215.High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling
Journal of Signal Processing Systems. 2016-03-05. DOI : 10.1007/s11265-016-1113-x.Comparison of high-throughput sequencing data compression tools
Nature Methods. 2016. DOI : 10.1038/nmeth.4037.An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values
2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs
Journal of Electrical and Computer Engineering. 2016-01-01. DOI : 10.1155/2016/8536432.Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.Automated Design Flow for Multi-Functional Dataflow-Based Platforms
Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.Analysis and optimization of dynamic dataflow programs
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.Actor Merging for Dataflow Process Networks
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.High-level synthesis of dataflow programs for heterogeneous platforms
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.TURNUS: an open-source design space exploration framework for dynamic stream programs
2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.MPEG high efficient video coding stream programming and many-cores scalability
2014.TURNUS: An open-source design space exploration framework for dynamic stream programs
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.Coarse grain clock gating of streaming applications in programmable logic implementations
2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.Characterizing communication behavior of dataflow programs using trace analysis
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms
2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations
2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.ECMA-407: A New 3D audio codec implementation up to NHK 22.2
2014. The 28th VDT International Convention 2014.ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL
2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6112.Optimizing Dataflow Programs for Hardware Synthesis
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http
2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures
2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.Methods to explore design space for MPEG RMC codec specifications
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.Reconfigurable media coding: An overview
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.Synthesis And Optimization Of High-Level Stream Programs
2013. 3rd Electronic System Level Synthesis Conference (ESLsyn), Austin, TX, MAY 31-JUN 01, 2013.Modeling Control Tokens for Composition of CAL Actors
2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS
2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624.Systems Design Space Exploration by Serial Dataflow Program Executions
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures
2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study
2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.Porting an MPEG-HEVC decoder to a low-power many-core platform
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.High-Level Synthesis of Dataflow Programs for Signal Processing Systems
2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.TURNUS: A design exploration framework for dataflow system design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.Synthesis and optimization of high-level stream programs
2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.Buffer optimization based on critical path analysis of a dataflow program design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.Live demonstration: High level software and hardware synthesis of dataflow programs
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.Secure Computing with the MPEG RVC Framework
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.Performance Benchmarking of RVC based Multimedia Specifications
2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem
2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.Representing Guard Dependencies in Dataflow Execution Traces
2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP
2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.Scheduling of dynamic dataflow programs based on state space analysis
2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.Profiling of Dataflow Programs Using Post Mortem Causation Traces
2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program
2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs
Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0396-6.Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs
2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework
2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.Scheduling of Dynamic Dataflow Programs with Model Checking
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.Methodology for the Hardware/Software Co-Design of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.MPEG Reconfigurable Video Representation
The MPEG Representation of Digital Media; Springer, 2011.Enseignement & Phd
Enseignement
Electrical and Electronics Engineering