Marco Mattavelli
Maître d'enseignement et de recherche
marco.mattavelli@epfl.ch +41 21 69 36984 http://gramm.epfl.ch/
EPFL SCI STI MM
ELB 141 (Bâtiment ELB)
Station 11
CH-1015 Lausanne
Unité: SEL-ENS
Publications
Les donées en-ligne ne sont pas accessibles
M. Zimmermann / J.-P. Thiran (Dir.) : Visual speech recognition. Lausanne, EPFL, 2018. DOI : 10.5075/epfl-thesis-8799.
A. A. Hernandez Lopez : Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis. 2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.
A. A. Hernandez Lopez : Transcriptome reconstruction with quality score distortion in reference-based alignment ; Research in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs; IEEE Transactions on Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2017.2774294.
S. Casale-Brunet; E. Bezati; M. Mattavelli : Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS). 2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.
M. Michalska; J. J. Ahmad; E. Bezati; S. Casale-Brunet; M. Mattavelli : Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.
M. Michalska; E. Bezati; S. Casale-Brunet; M. Mattavelli : Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms, 2017 25th European Signal Processing Conference (EUSIPCO). 2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.
S. Casale-Brunet; E. Bezati; M. Mattavelli : High level synthesis of Smith-Waterman dataflow implementations, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). 2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.
M. Hernaez; C. Alberti; M. Mattavelli; I. Ochoa : MPEG-G the emerging standard for genomic data compression. 2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.
A. A. Hernandez-Lopez; J. Voges; C. Alberti; M. Mattavelli; J. Ostermann : Differential gene expression with lossy compression of quality scores in RNA-seq data. 2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.
J. S. Rodriguez Estupiñan / Y. Leblebici; A. Vachoux (Dir.) : Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7649.
M. M. Michalska / M. Mattavelli (Dir.) : Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. Janneck : Trace-based manycore partitioning of stream-processing applications, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : High-level system synthesis and optimization of dataflow programs for MPSoCs, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.
M. Michalska; N. Zufferey; E. Bezati; M. Mattavelli : Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.
S. Casale-Brunet; E. Bezati; M. Mattavelli : Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.
E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. DOI : 10.1109/TCAD.2016.2597215.
E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). 2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.
K. Jerbi; H. Yviquel; A. Sanchez; D. Renzi; D. J. De Saint Jorre et al. : On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling; Journal of Signal Processing Systems. 2016-03-05. DOI : 10.1007/s11265-016-1113-x.
I. Numanagic; J. K. Bonfield; F. Hach; J. Voges; J. Ostermann et al. : Comparison of high-throughput sequencing data compression tools; Nature Methods. 2016. DOI : 10.1038/nmeth.4037.
C. Alberti; N. Daniels; M. Hernaez; J. Voges; R. L. Goldfeder et al. : An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values. 2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.
M. Michalska; N. Zufferey; M. Mattavelli : Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs; Journal Of Electrical And Computer Engineering. 2016. DOI : 10.1155/2016/8536432.
C. Massimo; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies; Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.
C. Sau; P. Meloni; L. Raffo; F. Palumbo; E. Bezati et al. : Automated Design Flow for Multi-Functional Dataflow-Based Platforms; Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.
M. Michalska; J. Boutellier; M. Mattavelli : A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.
A. Prihozhy; E. Bezati; A. A.-H. Ab Rahman; M. Mattavelli : Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.
S. Casale-Brunet / M. Mattavelli (Dir.) : Analysis and optimization of dynamic dataflow programs. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.
J. Boutellier; J. Ersfolk; J. Lilius; M. Mattavelli; G. Roquier et al. : Actor Merging for Dataflow Process Networks; Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.
E. Bezati / M. Mattavelli (Dir.) : High-level synthesis of dataflow programs for heterogeneous platforms. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.
S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. : TURNUS: an open-source design space exploration framework for dynamic stream programs. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.
M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.
S. Casale Brunet; E. Bezati; M. Mattavelli; M. Canale; J. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014. DOI : 10.1109/DASIP.2014.7115623.
D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. : MPEG high efficient video coding stream programming and many-cores scalability. 2014.
S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. : TURNUS: An open-source design space exploration framework for dynamic stream programs. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.
S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck : Coarse grain clock gating of streaming applications in programmable logic implementations. 2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.
J. W. Janneck; S. Casale-Brunet; M. Mattavelli : Characterizing communication behavior of dataflow programs using trace analysis. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.
D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet : Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. 2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.
M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.
C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. : Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations. 2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.
A. A.-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli : A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: A New 3D audio codec implementation up to NHK 22.2. 2014. The 28th VDT International Convention 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL. 2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.
A. Cevrero / Y. Leblebici; P. Ienne (Dir.) : Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6112.
A. A. H. B. Ab Rahman / M. Mattavelli (Dir.) : Optimizing Dataflow Programs for Hardware Synthesis. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.
E. Bezati; R. Thavot; G. Roquier; M. Mattavelli : High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms; Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.
C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http. 2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.
S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures. 2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.
S. Casale-Brunet; A. Elguindy; E. Bezati; R. Thavot; G. Roquier et al. : Methods to explore design space for MPEG RMC codec specifications; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.
E. S. Jang; M. Mattavelli; M. Preda; M. Raulet; H. Sun : Reconfigurable media coding: An overview; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Synthesis And Optimization Of High-Level Stream Programs. 2013. 3rd Electronic System Level Synthesis Conference (ESLsyn), Austin, TX, MAY 31-JUN 01, 2013.
J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Modeling Control Tokens for Composition of CAL Actors. 2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius : STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS. 2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620–2624.
S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck : Systems Design Space Exploration by Serial Dataflow Program Executions. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures. 2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.
A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli : Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study. 2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet : Porting an MPEG-HEVC decoder to a low-power many-core platform. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.
E. Bezati; M. Mattavelli; J. Janneck : High-Level Synthesis of Dataflow Programs for Signal Processing Systems. 2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.
S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. : Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : TURNUS: A design exploration framework for dataflow system design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck : Synthesis and optimization of high-level stream programs. 2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Buffer optimization based on critical path analysis of a dataflow program design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.
E. Bezati; G. Roquier; M. Mattavelli : Live demonstration: High level software and hardware synthesis of dataflow programs. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.
J. J. Ahmad; S. Li; R. Thavot; M. Mattavelli : Secure Computing with the MPEG RVC Framework; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.
J. J. Ahmad; S. Li; M. Mattavelli : Performance Benchmarking of RVC based Multimedia Specifications. 2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem. 2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Representing Guard Dependencies in Dataflow Execution Traces. 2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.
C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP. 2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.
R. Thavot / M. Mattavelli (Dir.) : High-level dataflow programming for complex digital systems. Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5628.
J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Scheduling of dynamic dataflow programs based on state space analysis. 2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Profiling of Dataflow Programs Using Post Mortem Causation Traces. 2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.
A. Rahman; A. A. H. Bin; R. Thavot; S. Casale Brunet; E. Bezati et al. : Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. 2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.
G. Roquier; E. Bezati; M. Mattavelli : Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs; Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.
G. Roquier; R. Thavot; M. Mattavelli : Methodology For The Hardware/Software Co-Design Of Dataflow Programs. 2011. IEEE Workshop on Signal Processing Systems (SiPS), Beirut, LEBANON, Oct 04-07, 2011. p. 174-179. DOI : 10.1109/SiPS.2011.6088970.
G. Roquier; E. Benzati; M. Mattavelli; J. W. Janneck : Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs. 2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.
J. J. Ahmad; S. Li; I. Amer; M. Mattavelli : Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework. 2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.
G. Roquier; E. Bezati; R. Thavot; M. Mattavelli : Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.
E. Bezati; H. Yviquel; M. Raulet; M. Mattavelli : A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.
C. Lucarz; M. Mattavelli; J. Janneck : Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.
J. Ersfolk; G. Roquier; F. Jokhio; J. Lilius; M. Mattavelli : Scheduling of Dynamic Dataflow Programs with Model Checking. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.
G. Roquier; R. Thavot; M. Mattavelli : Methodology for the Hardware/Software Co-Design of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.
M. Mattavelli : MPEG Reconfigurable Video Representation; The MPEG Representation of Digital Media; Springer, 2011.
A. Rahman; A. A. H. Bin; H. Amer; A. Prihozhy; C. Lucarz et al. : Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL. 2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.
H. Amer; A. Rahman; A. A. H. Bin; I. Amer; C. Lucarz et al. : Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder. 2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011.
A. Rahman; A. A. H. Bin; A. Prihozhy; M. Mattavelli : Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL; Eurasip Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-19.
C. Lucarz / M. Mattavelli (Dir.) : Dataflow Programming for Systems Design Space Exploration for Multicore Platforms. Lausanne, EPFL, 2011. DOI : 10.5075/epfl-thesis-5069.
R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description ; 2010.
A. Rahman; A. Al-Hadi; R. Thavot; M. Mattavelli; P. Faure : Hardware and software synthesis of image filters from CAL dataflow specification ; 2010.
R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli : Generation of Hardware/Software Systems Based on CAL Dataflow Description; Algorithm-Architecture Matching for Signal and Image Processing; http://www.springer.com/engineering/signals/book/978-90-481-9964-8?changeHeader: Springer, 2010. p. 275-292.
A. Rahman; A. A. H. Bin; R. Thavot; M. Mattavelli; P. Faure : Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
C. Lucarz; G. Roquier; M. Mattavelli : High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
E. Bezati; M. Mattavelli; M. Raulet : RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.
F. Palumbo; D. Pani; E. Manca; L. Raffo; M. Mattavelli et al. : RVC: a Multi-Decoder CAL Composer tool. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
J. W. Jannek; M. Mattavelli; M. Raulet; M. Wipliez : Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards. 2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010.
Infoscience
Les donées en-ligne ne sont pas accessiblesM. Zimmermann / J.-P. Thiran (Dir.) : Visual speech recognition. Lausanne, EPFL, 2018. DOI : 10.5075/epfl-thesis-8799.
A. A. Hernandez Lopez : Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis. 2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.
A. A. Hernandez Lopez : Transcriptome reconstruction with quality score distortion in reference-based alignment ; Research in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs; IEEE Transactions on Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2017.2774294.
S. Casale-Brunet; E. Bezati; M. Mattavelli : Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS). 2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.
M. Michalska; J. J. Ahmad; E. Bezati; S. Casale-Brunet; M. Mattavelli : Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.
M. Michalska; E. Bezati; S. Casale-Brunet; M. Mattavelli : Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms, 2017 25th European Signal Processing Conference (EUSIPCO). 2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.
S. Casale-Brunet; E. Bezati; M. Mattavelli : High level synthesis of Smith-Waterman dataflow implementations, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). 2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.
M. Hernaez; C. Alberti; M. Mattavelli; I. Ochoa : MPEG-G the emerging standard for genomic data compression. 2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.
A. A. Hernandez-Lopez; J. Voges; C. Alberti; M. Mattavelli; J. Ostermann : Differential gene expression with lossy compression of quality scores in RNA-seq data. 2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.
J. S. Rodriguez Estupiñan / Y. Leblebici; A. Vachoux (Dir.) : Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7649.
M. M. Michalska / M. Mattavelli (Dir.) : Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. Janneck : Trace-based manycore partitioning of stream-processing applications, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : High-level system synthesis and optimization of dataflow programs for MPSoCs, 2016 50th Asilomar Conference on Signals, Systems and Computers. 2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.
M. Michalska; N. Zufferey; E. Bezati; M. Mattavelli : Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.
S. Casale-Brunet; E. Bezati; M. Mattavelli : Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). 2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.
E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. DOI : 10.1109/TCAD.2016.2597215.
E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck : High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). 2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.
K. Jerbi; H. Yviquel; A. Sanchez; D. Renzi; D. J. De Saint Jorre et al. : On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling; Journal of Signal Processing Systems. 2016-03-05. DOI : 10.1007/s11265-016-1113-x.
I. Numanagic; J. K. Bonfield; F. Hach; J. Voges; J. Ostermann et al. : Comparison of high-throughput sequencing data compression tools; Nature Methods. 2016. DOI : 10.1038/nmeth.4037.
C. Alberti; N. Daniels; M. Hernaez; J. Voges; R. L. Goldfeder et al. : An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values. 2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.
M. Michalska; N. Zufferey; M. Mattavelli : Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs; Journal Of Electrical And Computer Engineering. 2016. DOI : 10.1155/2016/8536432.
C. Massimo; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies; Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.
C. Sau; P. Meloni; L. Raffo; F. Palumbo; E. Bezati et al. : Automated Design Flow for Multi-Functional Dataflow-Based Platforms; Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.
M. Michalska; J. Boutellier; M. Mattavelli : A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.
M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli : Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. 2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.
A. Prihozhy; E. Bezati; A. A.-H. Ab Rahman; M. Mattavelli : Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.
S. Casale-Brunet / M. Mattavelli (Dir.) : Analysis and optimization of dynamic dataflow programs. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.
J. Boutellier; J. Ersfolk; J. Lilius; M. Mattavelli; G. Roquier et al. : Actor Merging for Dataflow Process Networks; Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.
E. Bezati / M. Mattavelli (Dir.) : High-level synthesis of dataflow programs for heterogeneous platforms. Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.
S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. : TURNUS: an open-source design space exploration framework for dynamic stream programs. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.
M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.
S. Casale Brunet; E. Bezati; M. Mattavelli; M. Canale; J. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014. DOI : 10.1109/DASIP.2014.7115623.
D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. : MPEG high efficient video coding stream programming and many-cores scalability. 2014.
S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. : TURNUS: An open-source design space exploration framework for dynamic stream programs. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.
S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck : Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck : Coarse grain clock gating of streaming applications in programmable logic implementations. 2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.
J. W. Janneck; S. Casale-Brunet; M. Mattavelli : Characterizing communication behavior of dataflow programs using trace analysis. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.
D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet : Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. 2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.
M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck : Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. 2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.
C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. : Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. 2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations. 2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.
A. A.-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli : A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: A New 3D audio codec implementation up to NHK 22.2. 2014. The 28th VDT International Convention 2014.
J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. : ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL. 2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.
A. Cevrero / Y. Leblebici; P. Ienne (Dir.) : Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6112.
A. A. H. B. Ab Rahman / M. Mattavelli (Dir.) : Optimizing Dataflow Programs for Hardware Synthesis. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.
E. Bezati; R. Thavot; G. Roquier; M. Mattavelli : High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms; Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.
C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http. 2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.
S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures. 2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.
S. Casale-Brunet; A. Elguindy; E. Bezati; R. Thavot; G. Roquier et al. : Methods to explore design space for MPEG RMC codec specifications; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.
E. S. Jang; M. Mattavelli; M. Preda; M. Raulet; H. Sun : Reconfigurable media coding: An overview; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.
E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck : Synthesis And Optimization Of High-Level Stream Programs. 2013. 3rd Electronic System Level Synthesis Conference (ESLsyn), Austin, TX, MAY 31-JUN 01, 2013.
J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Modeling Control Tokens for Composition of CAL Actors. 2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius : STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS. 2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620–2624.
S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck : Systems Design Space Exploration by Serial Dataflow Program Executions. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.
S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. : Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures. 2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.
A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli : Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study. 2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.
D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet : Porting an MPEG-HEVC decoder to a low-power many-core platform. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.
E. Bezati; M. Mattavelli; J. Janneck : High-Level Synthesis of Dataflow Programs for Signal Processing Systems. 2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.
S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. : Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : TURNUS: A design exploration framework for dataflow system design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.
E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck : Synthesis and optimization of high-level stream programs. 2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Buffer optimization based on critical path analysis of a dataflow program design. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.
E. Bezati; G. Roquier; M. Mattavelli : Live demonstration: High level software and hardware synthesis of dataflow programs. 2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.
J. J. Ahmad; S. Li; R. Thavot; M. Mattavelli : Secure Computing with the MPEG RVC Framework; Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.
J. J. Ahmad; S. Li; M. Mattavelli : Performance Benchmarking of RVC based Multimedia Specifications. 2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems. 2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem. 2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.
S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck : Representing Guard Dependencies in Dataflow Execution Traces. 2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.
C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. : Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP. 2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.
R. Thavot / M. Mattavelli (Dir.) : High-level dataflow programming for complex digital systems. Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5628.
J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli : Scheduling of dynamic dataflow programs based on state space analysis. 2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.
S. Casale Brunet; M. Mattavelli; J. W. Janneck : Profiling of Dataflow Programs Using Post Mortem Causation Traces. 2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.
A. Rahman; A. A. H. Bin; R. Thavot; S. Casale Brunet; E. Bezati et al. : Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. 2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.
G. Roquier; E. Bezati; M. Mattavelli : Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs; Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.
G. Roquier; R. Thavot; M. Mattavelli : Methodology For The Hardware/Software Co-Design Of Dataflow Programs. 2011. IEEE Workshop on Signal Processing Systems (SiPS), Beirut, LEBANON, Oct 04-07, 2011. p. 174-179. DOI : 10.1109/SiPS.2011.6088970.
G. Roquier; E. Benzati; M. Mattavelli; J. W. Janneck : Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs. 2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.
J. J. Ahmad; S. Li; I. Amer; M. Mattavelli : Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework. 2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.
G. Roquier; E. Bezati; R. Thavot; M. Mattavelli : Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.
E. Bezati; H. Yviquel; M. Raulet; M. Mattavelli : A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems. 2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.
C. Lucarz; M. Mattavelli; J. Janneck : Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.
J. Ersfolk; G. Roquier; F. Jokhio; J. Lilius; M. Mattavelli : Scheduling of Dynamic Dataflow Programs with Model Checking. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.
G. Roquier; R. Thavot; M. Mattavelli : Methodology for the Hardware/Software Co-Design of Dataflow Programs. 2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.
M. Mattavelli : MPEG Reconfigurable Video Representation; The MPEG Representation of Digital Media; Springer, 2011.
A. Rahman; A. A. H. Bin; H. Amer; A. Prihozhy; C. Lucarz et al. : Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL. 2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.
H. Amer; A. Rahman; A. A. H. Bin; I. Amer; C. Lucarz et al. : Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder. 2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011.
A. Rahman; A. A. H. Bin; A. Prihozhy; M. Mattavelli : Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL; Eurasip Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-19.
C. Lucarz / M. Mattavelli (Dir.) : Dataflow Programming for Systems Design Space Exploration for Multicore Platforms. Lausanne, EPFL, 2011. DOI : 10.5075/epfl-thesis-5069.
R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description ; 2010.
A. Rahman; A. Al-Hadi; R. Thavot; M. Mattavelli; P. Faure : Hardware and software synthesis of image filters from CAL dataflow specification ; 2010.
R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli : Generation of Hardware/Software Systems Based on CAL Dataflow Description; Algorithm-Architecture Matching for Signal and Image Processing; http://www.springer.com/engineering/signals/book/978-90-481-9964-8?changeHeader: Springer, 2010. p. 275-292.
A. Rahman; A. A. H. Bin; R. Thavot; M. Mattavelli; P. Faure : Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli : Automatic mutli-connectivity interface generation for system designs based on a dataflow description. 2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
C. Lucarz; G. Roquier; M. Mattavelli : High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
E. Bezati; M. Mattavelli; M. Raulet : RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.
F. Palumbo; D. Pani; E. Manca; L. Raffo; M. Mattavelli et al. : RVC: a Multi-Decoder CAL Composer tool. 2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
J. W. Jannek; M. Mattavelli; M. Raulet; M. Wipliez : Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards. 2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010.
Enseignement & Phd
Enseignement
- Electrical and Electronics Engineering,
Programmes doctoraux
- Doctoral program in computer and communication sciences
- Doctoral Program in Microsystems and Microelectronics
- Doctoral Program in Electrical Engineering
Doctorants
Besirli Mustafa
Bloch Aurélien François Gilbert
Hernandez Lopez Ana Angelica
Aguirre Sylvain ...
Bezati Endri ...
Casale Brunet Simone ...
Clerc Christophe ...
Lucarz Christophe ...
Michalska Malgorzata Maria ...
Shao Beilu ...
Thavot Richard ...
Zhou Ruohua ...
Bloch Aurélien François Gilbert
Hernandez Lopez Ana Angelica
A dirigé les thèses de
Ab Rahman Ab Al Hadi Bin ...Aguirre Sylvain ...
Bezati Endri ...
Casale Brunet Simone ...
Clerc Christophe ...
Lucarz Christophe ...
Michalska Malgorzata Maria ...
Shao Beilu ...
Thavot Richard ...
Zhou Ruohua ...
Cours
Systems and architectures for signal processing
Etude des composants essentiels eessentiels et des technologies des systèmes de traitements des signaux et communications du point de vue théorique, algorithmique et d'implémentation. 