Marco Mattavelli
Maître d'enseignement et de recherche
marco.mattavelli@epfl.ch +41 21 693 69 84 http://gramm.epfl.ch/
Nationalité: Italian and Swiss
Date de naissance: 18.07.1961
EPFL SCI STI MM
ELB 141 (Bâtiment ELB)
Station 11
1015 Lausanne
+41 21 693 69 84
+41 21 693 69 81
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ELB 141
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Web site: Site web: https://gramm.epfl.ch/
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Publications
Publications Infoscience
Efficient Neural Clustering and Compression of Strings Through Approximate Euclidean Embeddings of the Levenshtein Distance
2024. Data Compression Conference, Snowbird, United States, 2024-03-19 - 2024-03-22. DOI : 10.1109/DCC58796.2024.00092.Self-indexing Algorithms for Graph Representations of Genomic References
Lausanne, EPFL, 2024. DOI : 10.5075/epfl-thesis-10994.Exploring blockchain-based metaverses: Data collection and valuation of virtual lands using machine learning techniques
DIGITAL BUSINESS. 2023. DOI : 10.1016/j.digbus.2023.100068.An Implantable Wireless System for Remote Hemodynamic Monitoring of Heart Failure Patients
Ieee Transactions On Biomedical Circuits And Systems. 2023. DOI : 10.1109/TBCAS.2023.3273711.Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2023. DOI : 10.1007/s11265-023-01884-6.Toward a common standard for data and specimen provenance in life sciences
Learning Health Systems. 2023. DOI : 10.1002/lrh2.10365.Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms
Lausanne, EPFL, 2023. DOI : 10.5075/epfl-thesis-9941.FM -Directories: Extending the Burrows-Wheeler Transform for String Labeled Vertex Graphs of (Almost) Arbitrary Topology
2023. Data Compression Conference (DCC), Snowbird, UT, Mar 21-24, 2023. p. 355 - 355. DOI : 10.1109/DCC55655.2023.00087.Integrated Electronics for Deep Implants to Remotely Monitor Hemodynamics
Lausanne, EPFL, 2023. DOI : 10.5075/epfl-thesis-9992.The impact of NFT profile pictures within social network communities
2022. GoodIT 2022: ACM International Conference on Information Technology for Social Good, Limassol, Cyprus, September 7 - 9, 2022. p. 283 - 291. DOI : 10.1145/3524458.3547230.Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution
Journal Of Low Power Electronics And Applications. 2022. DOI : 10.3390/jlpea12030036.Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis
Journal Of Low Power Electronics And Applications. 2022. DOI : 10.3390/jlpea12030040.An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems
IEEE Transactions on Biomedical Circuits and Systems. 2022. DOI : 10.1109/TBCAS.2022.3187828.Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms
2022. 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 20-23, 2021. p. 69 - 76. DOI : 10.1109/MCSoC51149.2021.00018.SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis
2022. 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 20-23, 2021. p. 62 - 68. DOI : 10.1109/MCSoC51149.2021.00017.MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments
2022. Data Compression Conference (DCC), Snowbird, UT, Mar 22-25, 2022. p. 478 - 478. DOI : 10.1109/DCC52660.2022.00089.A Capacitively-Coupled Chopper Instrumentation Amplifier for Implantable Bridge Sensor Systems
2022. 20th IEEE Interregional NEWCAS Conference (IEEE NEWCAS), Quebec City, CANADA, Jun 19-22, 2022. p. 208 - 212. DOI : 10.1109/NEWCAS52662.2022.9842137.An Implantable Inductive Sensor for Direct and Continuous Monitoring of the Pulmonary Artery Cross-Sectional Area
2022. 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan, October 13-15, 2022. p. 31 - 35. DOI : 10.1109/BioCAS54905.2022.9948566.Cardiovascular monitoring system
US2024115229 ; EP4287930 ; CN116829058 ; CA3207258 ; WO2022167382 ; EP4039173 . 2022.Inter-actions parallel execution on GPU from high-level dataflow synthesis
2022. 2021 55th Asilomar Conference on Signals, Systems, and Computers (ACSSC 2021), Pacific Grove, CA, USA, 31 Oct.-3 Nov. 2021. p. 1151 - 1155. DOI : 10.1109/IEEECONF53345.2021.9723288.A 0.4 nJ Excitation Energy Bridge-to-Digital Converter for Implantable Pulmonary Artery Pressure Monitoring
2021. 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), Berlin, Germany, October 7-9, 2021. DOI : 10.1109/BioCAS49922.2021.9644941.An Introduction to MPEG-G: The First Open ISO/IEC Standard for the Compression and Exchange of Genomic Sequencing Data
Proceedings of the IEEE. 2021. DOI : 10.1109/JPROC.2021.3082027.Methodologies for Synthesizing and Analyzing Dynamic Dataflow Programs in Heterogeneous Systems for Edge Computing
Ieee Open Journal Of Circuits And Systems. 2021. DOI : 10.1109/OJCAS.2021.3116342.Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem
2021. 4th IEEE International Conference on Blockchain (Blockchain), ELECTR NETWORK, Dec 06-08, 2021. p. 188 - 195. DOI : 10.1109/BLOCKCHAIN53845.2021.00033.Fully Soft-Switched High Step-Up Nonisolated Three-Port DC-DC Converter Using GaN HEMTs
Ieee Transactions On Industrial Electronics. 2020. DOI : 10.1109/TIE.2019.2944068.Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2020. DOI : 10.1007/s11265-020-01568-5.High Precision Capacitive Moisture Sensor for Polymers: Modeling and Experiments
IEEE Sensors Journal. 2020. DOI : 10.1109/JSEN.2019.2957108.Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis
2020. 2020 IEEE Workshop on Signal Processing Systems (SiPS), [Virtual Conference], October 20 - 22, 2020. p. 1 - 6. DOI : 10.1109/SiPS50750.2020.9195250.CMOS-Based Readout and Control Electronics for Microgrippers
2020. IEEE Sensors Conference, ELECTR NETWORK, Oct 25-28, 2020. DOI : 10.1109/SENSORS47125.2020.9278921.Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism
2019. Computational Science – ICCS 2019. p. 717 - 724. DOI : 10.1007/978-3-030-22750-0_70.Low-Cost Readout Electronics for Piezoresistive MEMS-Based Transducers
2019. IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Auckland, NEW ZEALAND, May 20-23, 2019. p. 1597 - 1601. DOI : 10.1109/I2MTC.2019.8826916.A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System
2019. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 261 - 264. DOI : 10.1109/PRIME.2019.8787811.Toward a Dynamic Threshold for Quality-Score Distortion in Reference-Based Alignment
2019. 15th International Symposium on Bioinformatics Research and Applications (ISBRA), Barcelona, Spain, June 3–6, 2019. p. 288 - 300. DOI : 10.1089/cmb.2019.0333.Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements
2019. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100 - 103. DOI : 10.1109/LAED.2019.8714730.An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms
2019. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1537 - 1541. DOI : 10.1109/ICASSP.2019.8682525.On the relevance of quality score metadata in genomic sequence data for omics applications
Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9812.Execution Trace Graph of Dataflow Process Networks
Ieee Transactions On Multi-Scale Computing Systems. 2018. DOI : 10.1109/TMSCS.2018.2790921.Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines
2018. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337 - 342. DOI : 10.1109/SiPS.2018.8598386.High Precision Capacitive Moisture Sensor for Polymers
2018. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212 - 215. DOI : 10.1109/ICSENS.2018.8589775.Shared-variable Synchronization Approaches for Dynamic Data Flow Programs
2018. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263 - 268. DOI : 10.1109/SiPS.2018.8598431.Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms
Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7607.MPEG-G the emerging standard for genomic data compression
2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.Differential gene expression with lossy compression of quality scores in RNA-seq data
2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444 - 444. DOI : 10.1109/Dcc.2017.75.On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling
Journal of Signal Processing Systems. 2016. DOI : 10.1007/s11265-016-1113-x.Comparison of high-throughput sequencing data compression tools
Nature Methods. 2016. DOI : 10.1038/nmeth.4037.Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs
Journal of Electrical and Computer Engineering. 2016. DOI : 10.1155/2016/8536432.An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values
2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA. DOI : 10.1109/Dcc.2016.39.Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443 - 1452. DOI : 10.1016/j.procs.2015.05.334.High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.Actor Merging for Dataflow Process Networks
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962 - 2966. DOI : 10.1016/j.procs.2015.05.498.Automated Design Flow for Multi-Functional Dataflow-Based Platforms
Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.Analysis and optimization of dynamic dataflow programs
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.ECMA-407: A New 3D audio codec implementation up to NHK 22.2
2014. The 28th VDT International Convention 2014.Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1 - 6. DOI : 10.1109/DASIP.2014.7115623.Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms
2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115 - 2119. DOI : 10.1109/ICIP.2014.7025424.Optimizing Dataflow Programs for Hardware Synthesis
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.TURNUS: An open-source design space exploration framework for dynamic stream programs
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1 - 2. DOI : 10.1109/DASIP.2014.7115614.Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59 - 66. DOI : 10.1109/SAMOS.2014.6893195.High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL
2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.MPEG high efficient video coding stream programming and many-cores scalability
2014.A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014. p. 5003 - 5007. DOI : 10.1109/ICASSP.2014.6854554.Characterizing communication behavior of dataflow programs using trace analysis
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44 - 50. DOI : 10.1109/SAMOS.2014.6893193.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1 - 6. DOI : 10.1109/SiPS.2014.6986054.Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations
2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014. DOI : 10.1109/ESLsyn.2014.6850387.Synthesis and optimization of high-level stream programs
2013. Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures
2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177 - 182. DOI : 10.1109/SiPS.2013.6674501.Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem
2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study
2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 63 - 70.Systems Design Space Exploration by Serial Dataflow Program Executions
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1805 - 1809. DOI : 10.1109/ACSSC.2013.6810613.TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 47 - 54.High-level dataflow programming for complex digital systems : methodology and tools for design, validation, and implementation
Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5628.Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 341 - 342.Reconfigurable media coding: An overview
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http
2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58 - 63. DOI : 10.1109/QoMEX.2013.6603211.Modeling Control Tokens for Composition of CAL Actors
2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 71 - 78.Buffer optimization based on critical path analysis of a dataflow program design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384 - 1387. DOI : 10.1109/ISCAS.2013.6572113.Live demonstration: High level software and hardware synthesis of dataflow programs
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.Performance Benchmarking of RVC based Multimedia Specifications
2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013. p. 4569 - 4573. DOI : 10.1109/ICIP.2013.6738941.Porting an MPEG-HEVC decoder to a low-power many-core platform
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.High-Level Synthesis of Dataflow Programs for Signal Processing Systems
2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013. p. 750 - 754. DOI : 10.1109/ISPA.2013.6703837.Secure Computing with the MPEG RVC Framework
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.Methods to explore design space for MPEG RMC codec specifications
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.TURNUS: A design exploration framework for dataflow system design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654 - 654. DOI : 10.1109/ISCAS.2013.6571927.Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP
2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013. p. 58 - 63. DOI : 10.1109/QoMEX.2013.6603211.Static and quasi-static compositions of stream processing applications from dynamic dataflow programs
2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620 - 2624. DOI : 10.1109/ICASSP.2013.6638130.Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1796 - 1800. DOI : 10.1109/ACSSC.2013.6810611.Representing Guard Dependencies in Dataflow Execution Traces
2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291 - 295. DOI : 10.1109/CICSYN.2013.26.Profiling of Dataflow Programs Using Post Mortem Causation Traces
2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220 - 225. DOI : 10.1109/SiPS.2012.54.Scheduling of dynamic dataflow programs based on state space analysis
2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661 - 1664. DOI : 10.1109/ICASSP.2012.6288215.Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs
Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program
2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 2012-10-25.Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL
2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs
2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL
Eurasip Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-19.Scheduling of Dynamic Dataflow Programs with Model Checking
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011. p. 37 - 42. DOI : 10.1109/SiPS.2011.6088946.Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011. p. 43 - 48. DOI : 10.1109/SiPS.2011.6088947.Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0389-5.Guest Editorial: Special Issue on Reconfigurable Guest Editorial: Special Issue on Reconfigurable Video Coding
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0418-4.Automatic synthesis of parsers and validation of bitstreams within the MPEG Reconfigurable Video Coding Framework
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0395-7.Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework
2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121 - 130. DOI : 10.1145/2037252.2037275.Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder
2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011. p. 186 - 191. DOI : 10.1109/SiPS.2011.6088972.Dataflow Programming for Systems Design Space Exploration for Multicore Platforms
Lausanne, EPFL, 2011. DOI : 10.5075/epfl-thesis-5069.MPEG Reconfigurable Video Representation
The MPEG Representation of Digital Media; Springer, 2011.Methodology for the Hardware/Software Co-Design of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011. p. 174 - 179. DOI : 10.1109/SiPS.2011.6088970.Automatic mutli-connectivity interface generation for system designs based on a dataflow description
2010Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification
2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.An adaptive system for real-time scalable video streaming with end- to-end qos control
2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 - 14, 2010.Automatic mutli-connectivity interface generation for system designs based on a dataflow description
2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.RVC: a Multi-Decoder CAL Composer tool
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.Generation of Hardware/Software Systems Based on CAL Dataflow Description
Algorithm-Architecture Matching for Signal and Image Processing; Dordrecht: Springer, 2010. p. 275 - 292.The reconfigurable video coding standard
IEEE Signal Processing Magazine. 2010. DOI : 10.1109/MSP.2010.936032.Hardware and software synthesis of image filters from CAL dataflow specification
2010MPEG Reconfigurable Video Coding
Handbook of Signal Processing Systems; Springer, 2010. p. 43 - 67.Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards
2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010. p. 223 - 234. DOI : 10.1145/1730836.1730864.Motion estimation accelerator with user search strategy for the RVC framework
2009. IEEE International Conference on Image Processing, Cairo, Egypt, November 7-10, 2009. p. 761 - 764. DOI : 10.1109/ICIP.2009.5414256.Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework
2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 - 24, 2009.Hardware synthesis of complex standard interfaces using CAL dataflow descriptions
2009. DASIP, Sophia Antipolis, September 22-24, 2009.Reconfigurable Video Coding : Objectives and Technologies
2009. IEEE International Conference on Image Processing, Cairo, Egypt: 2009, Cairo, Egypt, 7-10 November, 2009. p. 749 - 752. DOI : 10.1109/ICIP.2009.541427.Algorithm/Architecture Co-Exploration of Visual Computing: Overview and Future Perspectives
IEEE Transactions On Circuits And Systems For Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2031376.Reconfigurable Video coding on Multicore An overview of its main objectives
Ieee Signal Processing Magazine. 2009. DOI : 10.1109/MSP.2009.934107.A Computationally Efficient Method for Polyphonic Pitch Estimation
EURASIP Journal on Advances in Signal Processing. 2009. DOI : 10.1155/2009/729494.CAL Dataflow Components For an MPEG RVC AVC Baseline Encoder
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2009. DOI : 10.1007/s11265-009-0399-3.An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators
2009. ISCAS 2009, Taipei, Taiwan, May, 2009. p. 799 - 799. DOI : 10.1109/ISCAS.2009.5117876.Special Issue: Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms
IEEE Transactions on Circuits and Systems for Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2034438.Adaptation based scalable video delivery and management : system and architecture design
Lausanne, EPFL, 2009. DOI : 10.5075/epfl-thesis-4550.Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems. 2008. DOI : 10.1155/2008/597872.[ISO/IEC MPEG contribution] Update of Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework
2008Dataflow design of a co-processor architecture for image processing
2008. Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008.[ISO/IEC MPEG contribution] BSDL Description of MPEG-4 SP and AVC BP Bitstream Syntax for RVC Framework
2008[ISO/IEC MPEG contribution] Functional Units for RVC Toolbox: Variable Length Decoding
2008Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case Study
Design, Automation and Test in Europe (DATE08), Munich, Germany.How to Make Stream Processing More Mainstream
2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.[ISO/IEC MPEG contribution] Auto-generation of RVC Parser from BSDL Syntax Description: Variable Length Decoding
2008Dataflow/Actor-Oriented language for the design of complex signal processing systems
2008. Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, Bruxelles, Belgium, 24-26 November 2008. p. 168 - 175.Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework
2008. 2008 IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 1520 - 6130. DOI : 10.1109/SIPS.2008.4671778.[ISO/IEC MPEG contribution] Function Units for Conversion from Syntax to Sequence of Tokens: BTYPE
2008A Multimedia Terminal for Adaptation and End-to-end QoS Control
2008. IEEE International Conference on Multimedia & Expo (ICME 2008), Hannover, Germany, June 23-26, 2008. p. 433 - 436. DOI : 10.1109/ICME.2008.4607464.OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems
2008. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.Efficient Data Flow Variable Length Decoding Implementation for the MPEG Reconfigurable Video Coding Framework
2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 188 - 193. DOI : 10.1109/SIPS.2008.4671760.Video Decoder Reconfigurations and AVS Extensions in the New MPEG Reconfigurable Video Coding Framework
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2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443 - 1452. DOI : 10.1016/j.procs.2015.05.334.High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6653.Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. DOI : 10.1109/TCAD.2015.2427278.Actor Merging for Dataflow Process Networks
Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2411229.A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures
2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962 - 2966. DOI : 10.1016/j.procs.2015.05.498.Automated Design Flow for Multi-Functional Dataflow-Based Platforms
Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015. DOI : 10.1007/s11265-015-1026-0.Analysis and optimization of dynamic dataflow programs
Lausanne, EPFL, 2015. DOI : 10.5075/epfl-thesis-6663.Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
Journal of Signal Processing Systems. 2015. DOI : 10.1007/s11265-015-1083-4.ECMA-407: A New 3D audio codec implementation up to NHK 22.2
2014. The 28th VDT International Convention 2014.Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1 - 6. DOI : 10.1109/DASIP.2014.7115623.Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms
2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115 - 2119. DOI : 10.1109/ICIP.2014.7025424.Optimizing Dataflow Programs for Hardware Synthesis
Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.TURNUS: An open-source design space exploration framework for dynamic stream programs
2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1 - 2. DOI : 10.1109/DASIP.2014.7115614.Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59 - 66. DOI : 10.1109/SAMOS.2014.6893195.High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
Journal Of Real-Time Image Processing. 2014. DOI : 10.1007/s11554-013-0326-5.ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL
2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.MPEG high efficient video coding stream programming and many-cores scalability
2014.A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations
2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014. p. 5003 - 5007. DOI : 10.1109/ICASSP.2014.6854554.Characterizing communication behavior of dataflow programs using trace analysis
2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44 - 50. DOI : 10.1109/SAMOS.2014.6893193.Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1 - 6. DOI : 10.1109/SiPS.2014.6986054.Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations
2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014. DOI : 10.1109/ESLsyn.2014.6850387.Synthesis and optimization of high-level stream programs
2013. Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures
2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177 - 182. DOI : 10.1109/SiPS.2013.6674501.Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem
2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study
2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 63 - 70.Systems Design Space Exploration by Serial Dataflow Program Executions
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1805 - 1809. DOI : 10.1109/ACSSC.2013.6810613.TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 47 - 54.High-level dataflow programming for complex digital systems : methodology and tools for design, validation, and implementation
Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5628.Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework
2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 341 - 342.Reconfigurable media coding: An overview
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.008.Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http
2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58 - 63. DOI : 10.1109/QoMEX.2013.6603211.Modeling Control Tokens for Composition of CAL Actors
2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 71 - 78.Buffer optimization based on critical path analysis of a dataflow program design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384 - 1387. DOI : 10.1109/ISCAS.2013.6572113.Live demonstration: High level software and hardware synthesis of dataflow programs
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.Performance Benchmarking of RVC based Multimedia Specifications
2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013. p. 4569 - 4573. DOI : 10.1109/ICIP.2013.6738941.Porting an MPEG-HEVC decoder to a low-power many-core platform
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.High-Level Synthesis of Dataflow Programs for Signal Processing Systems
2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013. p. 750 - 754. DOI : 10.1109/ISPA.2013.6703837.Secure Computing with the MPEG RVC Framework
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.015.Methods to explore design space for MPEG RMC codec specifications
Signal Processing-Image Communication. 2013. DOI : 10.1016/j.image.2013.08.012.TURNUS: A design exploration framework for dataflow system design
2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654 - 654. DOI : 10.1109/ISCAS.2013.6571927.Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP
2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013. p. 58 - 63. DOI : 10.1109/QoMEX.2013.6603211.Static and quasi-static compositions of stream processing applications from dynamic dataflow programs
2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620 - 2624. DOI : 10.1109/ICASSP.2013.6638130.Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications
2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1796 - 1800. DOI : 10.1109/ACSSC.2013.6810611.Representing Guard Dependencies in Dataflow Execution Traces
2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291 - 295. DOI : 10.1109/CICSYN.2013.26.Profiling of Dataflow Programs Using Post Mortem Causation Traces
2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220 - 225. DOI : 10.1109/SiPS.2012.54.Scheduling of dynamic dataflow programs based on state space analysis
2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661 - 1664. DOI : 10.1109/ICASSP.2012.6288215.Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs
Journal of Electrical and Computer Engineering, Special issue on "ESL Design Methodology". 2012. DOI : 10.1155/2012/484962.Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program
2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 2012-10-25.Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL
2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs
2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems
2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL
Eurasip Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-19.Scheduling of Dynamic Dataflow Programs with Model Checking
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011. p. 37 - 42. DOI : 10.1109/SiPS.2011.6088946.Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011. p. 43 - 48. DOI : 10.1109/SiPS.2011.6088947.Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0389-5.Guest Editorial: Special Issue on Reconfigurable Guest Editorial: Special Issue on Reconfigurable Video Coding
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0418-4.Automatic synthesis of parsers and validation of bitstreams within the MPEG Reconfigurable Video Coding Framework
Journal of Signal Processing Systems. 2011. DOI : 10.1007/s11265-009-0395-7.Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework
2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121 - 130. DOI : 10.1145/2037252.2037275.Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder
2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011. p. 186 - 191. DOI : 10.1109/SiPS.2011.6088972.Dataflow Programming for Systems Design Space Exploration for Multicore Platforms
Lausanne, EPFL, 2011. DOI : 10.5075/epfl-thesis-5069.MPEG Reconfigurable Video Representation
The MPEG Representation of Digital Media; Springer, 2011.Methodology for the Hardware/Software Co-Design of Dataflow Programs
2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011. p. 174 - 179. DOI : 10.1109/SiPS.2011.6088970.Automatic mutli-connectivity interface generation for system designs based on a dataflow description
2010Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification
2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.An adaptive system for real-time scalable video streaming with end- to-end qos control
2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 - 14, 2010.Automatic mutli-connectivity interface generation for system designs based on a dataflow description
2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.RVC: a Multi-Decoder CAL Composer tool
2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.Generation of Hardware/Software Systems Based on CAL Dataflow Description
Algorithm-Architecture Matching for Signal and Image Processing; Dordrecht: Springer, 2010. p. 275 - 292.The reconfigurable video coding standard
IEEE Signal Processing Magazine. 2010. DOI : 10.1109/MSP.2010.936032.Hardware and software synthesis of image filters from CAL dataflow specification
2010MPEG Reconfigurable Video Coding
Handbook of Signal Processing Systems; Springer, 2010. p. 43 - 67.Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards
2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010. p. 223 - 234. DOI : 10.1145/1730836.1730864.Motion estimation accelerator with user search strategy for the RVC framework
2009. IEEE International Conference on Image Processing, Cairo, Egypt, November 7-10, 2009. p. 761 - 764. DOI : 10.1109/ICIP.2009.5414256.Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework
2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 - 24, 2009.Hardware synthesis of complex standard interfaces using CAL dataflow descriptions
2009. DASIP, Sophia Antipolis, September 22-24, 2009.Reconfigurable Video Coding : Objectives and Technologies
2009. IEEE International Conference on Image Processing, Cairo, Egypt: 2009, Cairo, Egypt, 7-10 November, 2009. p. 749 - 752. DOI : 10.1109/ICIP.2009.541427.Algorithm/Architecture Co-Exploration of Visual Computing: Overview and Future Perspectives
IEEE Transactions On Circuits And Systems For Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2031376.Reconfigurable Video coding on Multicore An overview of its main objectives
Ieee Signal Processing Magazine. 2009. DOI : 10.1109/MSP.2009.934107.A Computationally Efficient Method for Polyphonic Pitch Estimation
EURASIP Journal on Advances in Signal Processing. 2009. DOI : 10.1155/2009/729494.CAL Dataflow Components For an MPEG RVC AVC Baseline Encoder
Journal Of Signal Processing Systems For Signal Image And Video Technology. 2009. DOI : 10.1007/s11265-009-0399-3.An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators
2009. ISCAS 2009, Taipei, Taiwan, May, 2009. p. 799 - 799. DOI : 10.1109/ISCAS.2009.5117876.Special Issue: Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms
IEEE Transactions on Circuits and Systems for Video Technology. 2009. DOI : 10.1109/TCSVT.2009.2034438.Adaptation based scalable video delivery and management : system and architecture design
Lausanne, EPFL, 2009. DOI : 10.5075/epfl-thesis-4550.Smart camera based on embedded HW/SW coprocessor
EURASIP Journal on Embedded Systems. 2008. DOI : 10.1155/2008/597872.[ISO/IEC MPEG contribution] Update of Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework
2008Dataflow design of a co-processor architecture for image processing
2008. Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008.[ISO/IEC MPEG contribution] BSDL Description of MPEG-4 SP and AVC BP Bitstream Syntax for RVC Framework
2008[ISO/IEC MPEG contribution] Functional Units for RVC Toolbox: Variable Length Decoding
2008Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case Study
Design, Automation and Test in Europe (DATE08), Munich, Germany.How to Make Stream Processing More Mainstream
2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.[ISO/IEC MPEG contribution] Auto-generation of RVC Parser from BSDL Syntax Description: Variable Length Decoding
2008Dataflow/Actor-Oriented language for the design of complex signal processing systems
2008. Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, Bruxelles, Belgium, 24-26 November 2008. p. 168 - 175.Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework
2008. 2008 IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 1520 - 6130. DOI : 10.1109/SIPS.2008.4671778.[ISO/IEC MPEG contribution] Function Units for Conversion from Syntax to Sequence of Tokens: BTYPE
2008A Multimedia Terminal for Adaptation and End-to-end QoS Control
2008. IEEE International Conference on Multimedia & Expo (ICME 2008), Hannover, Germany, June 23-26, 2008. p. 433 - 436. DOI : 10.1109/ICME.2008.4607464.OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems
2008. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.Efficient Data Flow Variable Length Decoding Implementation for the MPEG Reconfigurable Video Coding Framework
2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 188 - 193. DOI : 10.1109/SIPS.2008.4671760.Video Decoder Reconfigurations and AVS Extensions in the New MPEG Reconfigurable Video Coding Framework
2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 164 - 169. DOI : 10.1109/SIPS.2008.4671756.Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework
2008. Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 182 - 187. DOI : 10.1109/SIPS.2008.4671759.Multimedia Terminal Architecture: An Inter-Operable Approach
2008. The First ACS/IEEE International Workshop on Wireless Internet Services (WISe'08) in conjunction with The Sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, April 1-4 2008. p. 981 - 986. DOI : 10.1109/AICCSA.2008.4493664.A co-design platform for Algorithm/Architecture design exploration
2008. IEEE International Conference on Multimedia & Expo, Hannover, Germany, June 23-26, 2008. p. 1069 - 1072. DOI : 10.1109/ICME.2008.4607623.A Multimedia Terminal for Adaptation and End-to-end QoS Control
2008. Proceedings of the IEEE International Conference on Multimedia & Expo (ICME 2008)., Hannover, Germany, 2008. p. 433 - 436. DOI : 10.1109/ICME.2008.4607464.Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework
2008. IEEE Workshop on Signal Processing Systems. SiPS 2008., Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 182 - 187. DOI : 10.1109/SIPS.2008.4671759.Music Onset Detection Based on Resonator Time Frequency Image
IEEE Transactions On Audio, Speech And Language Processing. 2008. DOI : 10.1109/TASL.2008.2002042.OpenDF – A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems
ACM SIGARCH Computer Architecture News. 2008. DOI : 10.1145/1556444.1556449.A Multimedia Terminal Supporting Adaptation for QoS Control
2008. 9th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS 2008), Klagenfurt, Austria, May 7-9, 2008. p. 113 - 116. DOI : 10.1109/WIAMIS.2008.54.Smart camera with embedded co-processor: a postal sorting application
2008. Optical and Digital Image Processing, Strasbourg, France, April 7 2008. DOI : 10.1117/12.781058.Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework
2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 293 - 298. DOI : 10.1109/SIPS.2008.4671778.Reconfigurable media coding: a new specification model for multimedia coders
2007. SiPS, Shanghai, China, October 17-19, 2007. p. 481 - 486. DOI : 10.1109/SIPS.2007.4387595.[ISO/IEC MPEG contribution] RVC Functional Units naming process proposal
2007A HW/SW codesign platform for Algorithm-Architecture mapping
2007. Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 27-29.[ISO/IEC MPEG contribution] A systematic procedure for the generation of a CAL parser from BDSL in the RVC framework - result CE 1.1
2007[ISO/IEC MPEG contribution] Compression of the RVC DDL Decoder Description with BiM (results of Core Experiment 1.3 in RVC)
2007[ISO/IEC MPEG contribution] Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework
2007[ISO/IEC MPEG contribution] Implementation of multiple reference frame support in RVC CAL model
2007[ISO/IEC MPEG contribution] Implement flexible FUs according to the processing mechanism in CVC WD using CAL (Results of Core Experiment 1.1) and analysis of the compactness of RVC Abstract Decoder Model (Results of Core Experiment 1.3)
2007[ISO/IEC MPEG contribution] A proposal for the classification and mapping of MPEG video coding technology into Functional Units for the RVC framework (Results of CE 2.2)
2007[ISO/IEC MPEG contribution] Serialized version of some MPEG-4 SP FUs
2007[ISO/IEC MPEG contribution] Update of the Textual specification of Functional Units, DDL and FUs SW of the MPEG-4 SP RVC Abstract Decoder Model (Results of CE 2.1)
2007A new time-frequency representation for music signal analysis: Resonator Time-Frequency Image
2007. 9th International Symposium on Signal Processing and its Applications, Sharjah, U ARAB EMIRATES, Feb 12-15, 2007. p. 1278 - 1281. DOI : 10.1109/ISSPA.2007.4555594.A profiling framework for high level design space exploration for memory and system architectures
Lausanne, EPFL, 2007. DOI : 10.5075/epfl-thesis-3706.A Simplified 8 × 8 Transformation And Quantization Real-Time Ip-Block For MPEG-4 H.264/AVC Applications: A New Design Flow Approach
Journal of Circuits, Systems, and Computers. 2007. DOI : 10.1142/S021812660700399X.A platform for mixed HW/SW algorithm specifications for the exploration of SW and HW partitioning
2007. PATMOS, Göteborg, Sweden, September 3-5, 2007. p. 485 - 494. DOI : 10.1007/978-3-540-74442-9_47.Reconfigurable Media Coding: Self-Describing Multimedia Bitstreams
2007. SIPS 2007, Shanghai, Oct. 17-19 2007. p. 319 - 324. DOI : 10.1109/SIPS.2007.4387565.[ISO/IEC MPEG contribution] Reconfigurability potential of the MPEG-4 SP decoder (results of CE 1.1)
2007High Performance Embedded Co-Processor Architecture For CMOS Imaging Systems
2007. Workshop on Design and Architectures for Signal and Image Processing, Grenoble (France), November 2007.Deep-submicron embedded processor architectures for high-performance, low-cost and low-power
Lausanne, EPFL, 2007. DOI : 10.5075/epfl-thesis-3742.[ISO/IEC MPEG contribution] Report on results of RVC CE 2.1 Reshape the current MPEG-4 SP CAL decoder according to the current FU interface in RVC WM
2006Feature extraction of musical content for automatic music transcription
Lausanne, EPFL, 2006. DOI : 10.5075/epfl-thesis-3638.[ISO/IEC MPEG contribution] Report on results of RVC CE 2.2: Explore the extensibility of FUs
2006SMIL to MPEG-4 BIFS Conversion
2006. The Second International Conference on Automated Production of Cross Media Content for Multi-Channel Distribution (AXMEDIS'06), Leeds, UK, December 13-15, 2006. p. 77 - 84. DOI : 10.1109/AXMEDIS.2006.49.EMBEDDED CO-PROCESSOR ARCHITECTURE & HARDWARE PROCESSING MODULES FOR CMOS BASED IMAGE ACQUISITION
2005.A Software/Hardware Platform For Rapid Prototyping of Video and Multimedia Designs
2005. IWSOC 2005, Banff, July 20-24, 2005. p. 30 - 33. DOI : 10.1109/IWSOC.2005.27.High-abstraction level complexity analysis and memory architecture simulations of multimedia algorithms
2005. JFAAA'2005, Dijon, January 18-21, 2005. p. 673 - 684. DOI : 10.1109/TCSVT.2005.846414.Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform
2005. IEEE International Conference on Image Processing, ICIP 2005, Genova, September 11-14, 2005. p. 591 - 594. DOI : 10.1109/ICIP.2005.1530573.A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs
2005. ICME 2005, Amsterdam, July 6-8, 2005. p. 872 - 875. DOI : 10.1109/ICME.2005.1521562.Introduction to the Special Issue on Integrated Multimedia Platforms
IEEE Transactions on Circuits and Systems for Video Technology. 2005. DOI : 10.1109/TCSVT.2005.846889.High abstraction Level Complexity Analysis: a Methodology and Tool for Extracting Architectural Information from generic C Algorithmic Descriptions
2005.High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions
2005. IWSOC, Banff, July 20-24, 2005. p. 304 - 307. DOI : 10.1109/IWSOC.2005.71.Evaluation of the parallelization potential for efficient multimedia implementations: Dynamics Evaluation of Algorithm Critical Path
IEEE Transactions on Circuits and Systems for Video Technology. 2005. DOI : 10.1109/TCSVT.2005.846427.Efficient error correction solutions for OFDM-based wireless video
2005. IEEE, PRIME 2005 Conference, Ph.D. Research In Micro-Electronics & Electronics, Lausanne, July 25-28, 2005. p. 205 - 208. DOI : 10.1109/RME.2005.1543040.Analyses of Critical Path and Parallelization Potential of MPEG-4 Reference Software
2004An automatic tool for high-level algorithmic complexity evaluation and optimization for system design
2004. Symposium on Design, Test, Integration and Packaging of MWMS/MOEMS, Montreux , SUISSE, May 12, 2004.Lossy compression of TPC data and trajectory tracking efficiency for the ALICE experiment
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. 2003. DOI : 10.1016/S0168-9002(03)00343-7.Net Algorithm Optimization, Proceedingss of Belarusian Engineering Academy
2003. p. 147 - 149.A Structured Description Language for Multimedia Content Protection
2003.Data Dependences Critical Path Evalutation at C/C++ System Level Description in Computer Science
Data Dependences Critical Path Evalutation at C/C++ System Level Description in Computer Science; Hermes, 2003.High-level algorithmic complexity evaluation for system design
Journal of Systems Architecture. 2003. DOI : 10.1016/S1383-7621(03)00038-9.Complexity evaluation, in depth analysis and possible optimization
2003.High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder
2003. 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings. p. 440 - 450. DOI : 10.1007/978-3-540-39762-5_50.Improving Dvb-T Forward Error Correction By Concatenated Turbo Code Scheme
2003.High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder
2003. p. 440 - 450. DOI : 10.1007/978-3-540-39762-5_50.Embedded co-processor architecture for CMOS based image acquisition
2003. International Conference on Image Processing, ICIP 2003, Barcelona, September 14-17, 2005. p. 591 - 594. DOI : 10.1109/ICIP.2003.1246749.Complexity evaluation of different configurations of JVT Codec
2003.Intellectual property management and protection for MPEG multimedia content: A structured language for interoperable IPMP systems
International Journal of Imaging Systems and Technology. 2003. DOI : 10.1002/ima.10070.Data Dependences Critical Path Evaluation at C/C++ System Level
2003. 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. p. 569 - 579. DOI : 10.1007/978-3-540-39762-5_63.Embedded Co-Processor Architecture for CMOS Based Image Acquisition
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1994.Motion estimation with violation of the constancy brightness constraint
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1993.Special Display Modes for HD-MAC Systems
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Enseignement
Electrical and Electronics Engineering